Ardavan Pedram

32 papers A* 6C 2Journal 15Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	DFModel: Design Space Optimization of Large-Scale Systems Exploiting Dataflow Mappings. CoRR Sho Ko, Nathan Zhang, Olivia Hsu, Ardavan Pedram, Kunle Olukotun
2023	J	`jnl`	Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network. CoRR Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
2022	J	`jnl`	Algorithm/architecture solutions to improve beyond uniform quantization in embedded DNN accelerators. J. Syst. Archit. Ardavan Pedram, Ali Shafiee Ardestani, Ling Li, Hamzah Abdel-Aziz, Jun Fang, Joseph Hassoun
2022	A*	`conf`	Griffin: Rethinking Sparse Optimization for Deep Learning Architectures. HPCA Jong Hoon Shin, Ali Shafiee, Ardavan Pedram, Hamzah Abdel-Aziz, Ling Li, Joseph Hassoun
2021	J	`jnl`	Design Space Exploration of Sparse Accelerators for Deep Neural Networks. CoRR Jong Hoon Shin, Ali Shafiee, Ardavan Pedram, Hamzah Abdel-Aziz, Ling Li, Joseph Hassoun
2021	—	`conf`	Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators. MLSys Hamzah Abdel-Aziz, Ali Shafiee, Jong Hoon Shin, Ardavan Pedram, Joseph Hassoun
2021	J	`jnl`	Rethinking Floating Point Overheads for Mixed Precision DNN Accelerators. CoRR Hamzah Abdel-Aziz, Ali Shafiee, Jong Hoon Shin, Ardavan Pedram, Joseph H. Hassoun
2020	J	`jnl`	Campfire: Compressible, Regularization-Free, Structured Sparse Training for Hardware Accelerators. CoRR Noah Gamboa, Kais Kudrolli, Anand Dhoot, Ardavan Pedram
2018	J	`jnl`	Plasticine: A Reconfigurable Accelerator for Parallel Patterns. IEEE Micro Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matthew Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun
2018	A*	`conf`	Spatial: a language and compiler for application accelerators. PLDI David Koeplinger, Matthew Feldman, Raghu Prabhakar, Yaqi Zhang, Stefan Hadjis, Ruben Fiszel, Tian Zhao, Luigi Nardi, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun
2017	J	`jnl`	CATERPILLAR: Coarse Grain Reconfigurable Architecture for Accelerating the Training of Deep Neural Networks. CoRR Yuanfang Li, Ardavan Pedram
2017	—	`conf`	CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks. ASAP Yuanfang Li, Ardavan Pedram
2017	J	`jnl`	Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. IEEE Des. Test Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, Shahar Kvatinsky
2017	A*	`conf`	Plasticine: A Reconfigurable Architecture For Parallel Paterns. ISCA Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matthew Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun
2016	J	`jnl`	A Systematic Approach to Blocking Convolutional Neural Networks. CoRR Xuan Yang, Jing Pu, Blaine Burton Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan-Kelley, Ardavan Pedram, Mark Horowitz
2016	J	`jnl`	Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. CoRR Ardavan Pedram, Stephen Richardson, Sameh Galal, Shahar Kvatinsky, Mark Horowitz
2016	—	`conf`	Deep compression and EIE: Efficient inference engine on compressed deep neural network. Hot Chips Symposium Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, Bill Dally
2016	A*	`conf`	EIE: Efficient Inference Engine on Compressed Deep Neural Network. ISCA Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
2016	J	`jnl`	EIE: Efficient Inference Engine on Compressed Deep Neural Network. CoRR Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
2016	A*	`conf`	Evaluating programmable architectures for imaging and vision applications. MICRO Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz
2016	A*	`conf`	Improving energy efficiency of DRAM by exploiting half page row access. MICRO Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz
2016	—	`conf`	Simulator calibration for accelerator-rich architecture studies. SAMOS Mochamad Asri, Ardavan Pedram, Lizy K. John, Andreas Gerstlauer
2014	J	`jnl`	A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores. J. Signal Process. Syst. Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer
2014	J	`jnl`	Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator. IEEE Trans. Computers Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn
2013	—	`conf`	Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics. IPDPS Workshops Ardavan Pedram
2013	C	`conf`	Floating Point Architecture Extensions for Optimized Matrix Factorization. IEEE Symposium on Computer Arithmetic Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn
2013	—	`conf`	Transforming a linear algebra core to an FFT accelerator. ASAP Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer
2012	—	`conf`	A Linear Algebra Core Design for Efficient Level-3 BLAS. ASAP Ardavan Pedram, Syed Zohaib Gilani, Nam Sung Kim, Robert A. van de Geijn, Michael J. Schulte, Andreas Gerstlauer
2012	J	`jnl`	Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures. IEEE Trans. Computers Ardavan Pedram, Robert A. van de Geijn, Andreas Gerstlauer
2012	C	`conf`	On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators. SBAC-PAD Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn
2011	—	`conf`	A high-performance, low-power linear algebra core. ASAP Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn
2009	—	`conf`	Modeling Cache Effects at the Transaction Level. IESS Ardavan Pedram, David Craven, Andreas Gerstlauer