Arda Yurdakul

51 papers A 1B 3C 8Journal 25Unranked 13
YearRankTypeTitle / Venue / Authors
2024 J jnl
Common Subexpression-Based Compression and Multiplication of Sparse Constant Matrices.
IEEE Embed. Syst. Lett.
Emre Bilgili, Arda Yurdakul
2024 J jnl
EdgeConvEns: Convolutional Ensemble Learning for Edge Intelligence.
IEEE Access
Ilkay Sikdokur, Inci M. Baytas, Arda Yurdakul
2023 J jnl
Common Subexpression-based Compression and Multiplication of Sparse Constant Matrices.
CoRR
Emre Bilgili, Arda Yurdakul
2023 C conf
Container Scheduling Under ARINC 653 Scheduler Constraints.
DSD
Mehmet Sirin Onen, Arda Yurdakul
2023 J jnl
EdgeConvEns: Convolutional Ensemble Learning for Edge Intelligence.
CoRR
Ilkay Sikdokur, Inci M. Baytas, Arda Yurdakul
2023 J jnl
ElectAnon: A Blockchain-based, Anonymous, Robust, and Scalable Ranked-choice Voting Protocol.
Distributed Ledger Technol. Res. Pract.
Ceyhun Onur, Arda Yurdakul
2022 C conf
A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning.
DSD
Cem Caglayan, Arda Yurdakul
2022 — conf
A Decentralized Framework with Dynamic and Event-Driven Container Orchestration at the Edge.
iThings/GreenCom/CPSCom/SmartData/Cybermatics
Umut Can Özyar, Arda Yurdakul
2022 J jnl
A Decentralized Framework with Dynamic and Event-Driven Container Orchestration at the Edge.
CoRR
Umut Can Özyar, Arda Yurdakul
2022 J jnl
ElectAnon: A Blockchain-Based, Anonymous, Robust and Scalable Ranked-Choice Voting Protocol.
CoRR
Ceyhun Onur, Arda Yurdakul
2022 J jnl
Image Classification on Accelerated Neural Networks.
CoRR
Ilkay Sikdokur, Inci M. Baytas, Arda Yurdakul
2021 — conf
SIMDify: Framework for SIMD-Processing with RISC-V Scalar Instruction Set.
ACSW
Mehmet Alp Sarkisla, Arda Yurdakul
2020 J jnl
An Embedded RISC-V Core with Fast Modular Multiplication.
CoRR
Ömer Faruk Irmak, Arda Yurdakul
2020 B conf
Model-based Design of a Roadside Unit for Emergency and Disaster Management.
NOMS
Nur Hilal, Arda Yurdakul
2019 J jnl
Designing a Blockchain-Based IoT With Ethereum, Swarm, and LoRa: The Software Solution to Create High Availability With Minimal Security Risks.
IEEE Consumer Electron. Mag.
Kazim Rifat Ozyilmaz, Arda Yurdakul
2018 J jnl
Customizable embedded processor array for multimedia applications.
Integr.
Mehmet Tükel, Arda Yurdakul, Berna Örs
2018 J jnl
Designing a blockchain-based IoT infrastructure with Ethereum, Swarm and LoRa.
CoRR
Kazim Rifat Ozyilmaz, Arda Yurdakul
2018 — conf
IDMoB: IoT Data Marketplace on Blockchain.
CVCBT
Kazim Rifat Ozyilmaz, Mehmet Dogan, Arda Yurdakul
2018 J jnl
IDMoB: IoT Data Marketplace on Blockchain.
CoRR
Kazim Rifat Özyilmaz, Mehmet Dogan, Arda Yurdakul
2018 B conf
WIP: Daily Life Oriented Indoor Localization by Fusion of Smartphone Sensors and Wi-Fi.
SMARTCOMP
Ayse Vildan Nurdag, Bert Arnrich, Arda Yurdakul
2017 J jnl
AxleDB: A novel programmable query processing platform on FPGA.
Microprocess. Microsystems
Behzad Salami, Gorker Alp Malazgirt, Oriol Arcas-Abella, Arda Yurdakul, Nehir Sönmez
2017 — conf
Integrating low-power IoT devices to a blockchain-based infrastructure: work-in-progress.
EMSOFT Companion
Kazim Rifat Özyilmaz, Arda Yurdakul
2017 J jnl
Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures.
J. Syst. Archit.
Gorker Alp Malazgirt, Arda Yurdakul
2016 — conf
An efficient mapping algorithm on 2-D mesh Network-on-Chip with reconfigurable switches.
DTIS
Salih Bayar, Arda Yurdakul
2016 — ch.
Big Data and HPC Acceleration with Vivado HLS.
FPGAs for Software Programmers
Moritz Schmid, Christian Schmitt, Frank Hannig, Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Adrián Cristal
2016 J jnl
Taxim: A Toolchain for Automated and Configurable Simulation for Embedded Multiprocessor Design.
CoRR
Gorker Alp Malazgirt, Deniz Candas, Arda Yurdakul
2015 A conf
Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only).
FPGA
Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Osman S. Unsal, Adrián Cristal
2015 J jnl
Customizing VLIW processors from dynamically profiled execution traces.
Microprocess. Microsystems
Gorker Alp Malazgirt, Arda Yurdakul, Smaïl Niar
2015 C conf
Exploring Embedded Symmetric Multiprocessing with Various On-Chip Architectures.
EUC
Gorker Alp Malazgirt, Bora Kiyan, Deniz Candas, Kamil Erdayandi, Arda Yurdakul
2015 — conf
High Level Synthesis Based Hardware Accelerator Design for Processing SQL Queries.
FPGAworld
Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Adrián Cristal, Osman S. Unsal
2015 J jnl
PFMAP: Exploitation of Particle Filters for Network-on-Chip Mapping.
IEEE Trans. Very Large Scale Integr. Syst.
Salih Bayar, Arda Yurdakul
2014 — conf
A dynamically reconfigurable architecture for emergency and disaster management in ITS.
ICCVE
Smaïl Niar, Arda Yurdakul, Osman S. Unsal, Tuna Tugcu, Aziz C. Yücetürk
2014 — conf
An Efficient Heterogeneous Register File Implementation for FPGAs.
IPDPS Workshops
Hasan Erdem Yantir, Arda Yurdakul
2014 B conf
Application specific multi-port memory customization in FPGAs.
FPL
Gorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smaïl Niar
2014 — conf
MIPT: Rapid exploration and evaluation for migrating sequential algorithms to multiprocessing systems with multi-port memories.
HPCS
Gorker Alp Malazgirt, Arda Yurdakul, Smaïl Niar
2013 C conf
Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs.
DSD
Hasan Erdem Yantir, Salih Bayar, Arda Yurdakul
2012 J jnl
A Heterogeneous Simulation and Modeling Framework for Automation Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dogan Fennibay, Arda Yurdakul, Alper Sen
2012 C conf
A Verifiable High Level Data Path Synthesis Framework.
DSD
Gorker Alp Malazgirt, Ender Culha, Alper Sen, I. Faik Baskaya, Arda Yurdakul
2012 J jnl
A dynamically reconfigurable communication architecture for multicore embedded systems.
J. Syst. Archit.
Salih Bayar, Arda Yurdakul
2012 — conf
High-Level verifiable data-path Synthesis for DSP systems.
SIU
Ender Culha, Gorker Alp Malazgirt, I. Faik Baskaya, Alper Sen, Arda Yurdakul
2011 — conf
A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs.
ReCoSoC
Salih Bayar, Mehmet Tükel, Arda Yurdakul
2010 C conf
Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems.
CIT
Dogan Fennibay, Arda Yurdakul, Alper Sen
2009 C conf
Design automation model for application-specific processors on reconfigurable fabric.
FDL
Bayram Kurumahmut, Gökhan Kabukcu, Roza Ghamari, Arda Yurdakul
2009 — conf
Halftoning soft cores for low-cost digital displays.
ISCIS
Muhammet Erkoc, Arda Yurdakul
2008 J jnl
An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mustafa Aktan, Arda Yurdakul, Günhan Dündar
2007 J jnl
Low-cost solution to on-line color filter array demosaicking.
Int. J. Imaging Syst. Technol.
Gökhan Kabukcu, Arda Yurdakul
2006 — conf
SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-Core.
SoC
Nehir Sönmez, Arda Yurdakul
2005 J jnl
Multiplierless implementation of 2-D FIR filters.
Integr.
Arda Yurdakul
2000 C conf
A synthesis tool for the multiplierless realization of FIR-based multirate DSP systems.
ISCAS
Arda Yurdakul
1999 J jnl
Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions.
J. VLSI Signal Process.
Arda Yurdakul, Günhan Dündar
1999 J jnl
Statistical methods for the estimation of quantization effects in FIR-based multirate systems.
IEEE Trans. Signal Process.
Arda Yurdakul, Günhan Dündar