Arani Sinha

38 papers A 9B 1Misc 15Journal 4Unranked 9
YearRankTypeTitle / Venue / Authors
2026 J jnl
Methodical Detection of Silent Data Errors From Foundry to Fleet.
IEEE Micro
Manu Shamsa, David P. Lerner, Arani Sinha, Thiago Macieira, Yogesh Varma
2026 J jnl
Silent Data Corruption in Artificial Intelligence: A Growing Challenge for Large-Scale Machine Learning.
IEEE Micro
Nishant George, Sudhanva Gurumurthi, Vilas Sridharan, Harish Dattatraya Dixit, Emel Goksu, Bharath Parthasarathy, Amber Huffman, Thiago Macieira, Arani Sinha, Dean Liberty, Lisa Minwell, Robert S. Chappell
2025 A conf
Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance.
ITC
Gowsika Dharmaraj, Abhijit Chatterjee, Adit D. Singh, Arani Sinha
2025 Misc conf
Special Session: Trustworthy Hardware-AI at the Cloud.
VTS
Francesco Angione, Paolo Bernardi, Alberto Bosio, Harish Dattatraya Dixit, Salvatore Pappalardo, Annachiara Ruospo, Ernesto Sánchez, Arani Sinha, Vittorio Turco
2024 A conf
Functional State Extraction using Scan DFT.
ITC
Ilya Wagner, Pankaj Pant, Arani Sinha
2024 — conf
Generating Storage-Aware Test Sets Targeting Several Fault Models.
ISVLSI
Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
2024 Misc conf
Innovative Practices Track: Session 2 Silent Data Corruption.
VTS
Arani Sinha, Adit D. Singh
2024 Misc conf
Innovative Practices Track: Session 3 Test and Functional Safety Standards.
VTS
Arani Sinha
2024 Misc conf
Innovative Practices Track: Session 4 AI Applications in Test.
VTS
Arani Sinha, Stefano Di Carlo
2023 A conf
Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure.
ITC
Arani Sinha, Glenn Colón-Bonet, Michael Fahy, Pankaj Pant, Haijing Mao, Akhilesh Shukla
2022 Misc conf
Innovative Practices Track: Next Generation Test Standards.
VTS
Arani Sinha
2022 Misc conf
Innovative Practices Track: Silent Data Errors.
VTS
Arani Sinha
2022 A conf
Multi-die Parallel Test Fabric for Scalability and Pattern Reusability.
ITC
Arani Sinha, Yonsang Cho, Jon Easter, Meizel V. Leiva Rojas
2022 — conf
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults.
ATS
Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman
2021 B conf
Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction.
ETS
Sandip Ray, Arani Sinha
2021 Misc conf
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.
VTS
Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
2020 A conf
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.
ITC
Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
2020 J jnl
Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests.
IEEE Des. Test
Ankit Shah, Raman Nayyar, Arani Sinha
2019 — conf
Analog/Mixed Signal IP DFx from a Foundry perspective.
LATS
Salem Abdennadher, Arani Sinha, Yonghyun Kim
2019 A conf
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.
ITC
Sujay Pandey, Sanya Gupta, Madhu Sudhan L., Suriya Natarajan, Arani Sinha, Abhijit Chatterjee
2019 J jnl
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.
ACM Trans. Design Autom. Electr. Syst.
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
2019 A conf
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.
DATE
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
2019 Misc conf
Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests.
VTS
Ankit Shah, Raman Nayyar, Arani Sinha
2017 A conf
DFM-aware fault model and ATPG for intra-cell and inter-cell defects.
ITC
Arani Sinha, Sujay Pandey, Ayush Singhal, Alodeep Sanyal, Alan Schmaltz
2017 Misc conf
Innovative practices session 1C screening for layout sensitive defects.
VTS
Arani Sinha, Nitin Chaudhary
2013 Misc conf
Path selection based on static timing analysis considering input necessary assignments.
VTS
Bo Yao, Arani Sinha, Irith Pomeranz
2011 Misc conf
A Novel mechanism for speed characterization during delay test.
VTS
Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou
2011 Misc conf
The bang for the buck with resiliency: Yield or field?
VTS
Arani Sinha, Suriyaprakash Natarajan
2011 Misc conf
The buck stops with wafer test: Dream or reality?
VTS
Suriyaprakash Natarajan, Arani Sinha
2010 Misc conf
Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?
VTS
Arani Sinha
2009 Misc conf
Panel: Analog Characterization and Test: The Long Road to Realization.
VTS
Arani Sinha, Amitava Majumdar, Vasu Ganti
2008 — conf
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults.
ATS
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
2007 — conf
On-Chip Inductance in X Architecture Enabled Design.
ISQED
Santosh Shah, Arani Sinha, Li Song, Narain D. Arora
2006 — conf
Simulating the Effects of Process Variations on Capacitive Crosstalk.
ICECS
Arani Sinha, Shahin Nazarian, T. M. Mak
2003 — conf
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults.
Asian Test Symposium
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
1999 — conf
Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction.
CICC
Arani Sinha, Salim Chowdhury
1999 A conf
Validation and test generation for oscillatory noise in VLSI interconnects.
ICCAD
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
1994 — conf
Location of the Largest Empty Rectangle among Arbitrary Obstacles.
FSTTCS
Subhas C. Nandy, Arani Sinha, Bhargab B. Bhattacharya