Aporva Amarnath

27 papers A* 5A 4B 1Journal 13Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
EPOCHS-1: A 12 nm Highly Heterogeneous Open-Source SoC With Distributed Coin-Based Power Management and Integrated Hybrid Voltage Regulation.
IEEE J. Solid State Circuits
Joseph Zuckerman, Martin Cochet, Maico Cassel dos Santos, Erik Jens Loscalzo, Karthik Swaminathan, Tianyu Jia, Davide Giri, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Samira Zaliasl, Michael Lekas, Stephen Cahill, Hesam Sadeghi, Joseph Meyer, Noah Sturcken, Sarita V. Adve, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Pradip Bose, Luca P. Carloni
2025 A* conf
ARTEMIS: Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era.
HPCA
Subhankar Pal, Aporva Amarnath, Behzad Boroujerdian, Augusto Vega, Alper Buyuktosunoglu, John-David Wellman, Vijay Janapa Reddi, Pradip Bose
2025 A* conf
FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications.
HPCA
Yongmo Park, Aporva Amarnath, Subhankar Pal, Karthik Swaminathan, Alper Buyuktosunoglu, Hayim Shaul, Ehud Aharoni, Nir Drucker, Wei D. Lu, Omri Soceanu, Pradip Bose
2025 — conf
MEADOW: Memory-efficient Dataflow and Data Packing for Low Power Edge LLMs.
MLSys
Abhishek Moitra, Arkapravo Ghosh, Shrey Agrawal, Aporva Amarnath, Karthik Swaminathan, Priyadarshini Panda
2025 J jnl
MEADOW: Memory-efficient Dataflow and Data Packing for Low Power Edge LLMs.
CoRR
Abhishek Moitra, Arkapravo Ghosh, Shrey Agarwal, Aporva Amarnath, Karthik Swaminathan, Priyadarshini Panda
2025 A conf
No Time to Lose: Enabling Real-Time Fluorescence Lifetime Imaging on Resource-constrained FPGAs Through Efficient Scheduling.
FPGA
Ismail Erbas, Aporva Amarnath, Vikas Pandey, Karthik Swaminathan, Naigang Wang, Xavier Intes
2024 — conf
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
ISSCC
Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei
2024 J jnl
A Neuro-Symbolic Approach to Multi-Agent RL for Interpretability and Probabilistic Decision Making.
CoRR
Chitra Subramanian, Miao Liu, Naweed Khan, Jonathan Lenchner, Aporva Amarnath, Sarathkrishna Swaminathan, Ryan Riegel, Alexander Gray
2024 J jnl
Compressing Recurrent Neural Networks for FPGA-accelerated Implementation in Fluorescence Lifetime Imaging.
CoRR
Ismail Erbas, Vikas Pandey, Aporva Amarnath, Naigang Wang, Karthik Swaminathan, Stefan T. Radev, Xavier Intes
2024 J jnl
Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms.
IEEE Comput. Archit. Lett.
Yongmo Park, Subhankar Pal, Aporva Amarnath, Karthik Swaminathan, Wei D. Lu, Alper Buyuktosunoglu, Pradip Bose
2024 J jnl
Unlocking Real-Time Fluorescence Lifetime Imaging: Multi-Pixel Parallelism for FPGA-Accelerated Processing.
CoRR
Ismail Erbas, Aporva Amarnath, Vikas Pandey, Karthik Swaminathan, Naigang Wang, Xavier Intes
2022 J jnl
A Holistic Solution for Reliability of 3D Parallel Systems.
ACM J. Emerg. Technol. Comput. Syst.
Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski
2022 J jnl
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs.
CoRR
Aporva Amarnath, Subhankar Pal, Hiwot Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald G. Dreslinski, Pradip Bose
2021 J jnl
A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors.
ACM J. Emerg. Technol. Comput. Syst.
Heewoo Kim, Aporva Amarnath, Javad Bagherzadeh, Nishil Talati, Ronald G. Dreslinski
2021 J jnl
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles.
IEEE Comput. Archit. Lett.
Aporva Amarnath, Subhankar Pal, Hiwot Tadese Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald Dreslinski Jr., Pradip Bose
2021 A* conf
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.
MICRO
Subhankar Pal, Aporva Amarnath, Siying Feng, Michael F. P. O'Boyle, Ronald G. Dreslinski, Christophe Dubach
2020 J jnl
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits
Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2020 A* conf
R2D3: A Reliability Engine for 3D Parallel Systems.
DAC
Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski
2020 J jnl
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
CoRR
Augusto Vega, Aporva Amarnath, John-David Wellman, Hiwot Kassa, Subhankar Pal, Hubertus Franke, Alper Buyuktosunoglu, Ronald G. Dreslinski, Pradip Bose
2020 A conf
Sparse-TPU: adapting systolic arrays for sparse matrices.
ICS
Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge
2020 B conf
Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.
PACT
Subhankar Pal, Siying Feng, Dong-Hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael F. P. O'Boyle, Murray Cole, Chaitali Chakrabarti, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski
2019 A conf
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology.
ISLPED
Aporva Amarnath, Javad Bagherzadeh, Jielun Tan, Ronald G. Dreslinski
2019 — conf
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
VLSI Circuits
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
2019 — conf
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
VLSI Circuits
Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2018 A* conf
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.
HPCA
Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2018 J jnl
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro
Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor
2017 A conf
A carbon nanotube transistor based RISC-V processor using pass transistor logic.
ISLPED
Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski