Anzhela Yu. Matrosova

44 papers C 7Journal 5Unranked 32

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	Deriving FSM-based tests using $a, b-\text{faults}$ for Logic Circuits. ISVLSI Andrey Laputenko, Nina Yevtushenko, Valentina Andreeva, Anzhela Yu. Matrosova
2021	—	`conf`	Applying Incompletely Specified Boolean Functions for Patch Circuit Generation. EWDTS Anzhela Yu. Matrosova, V. Provkin
2021	J	`jnl`	Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits. Autom. Remote. Control. Anzhela Yu. Matrosova, Semen Chernyshov, O. Kh. Kim, Ekaterina Nikolaeva
2020	—	`conf`	Masking Internal Node Logical Faults and Trojan Circuits Injections with Using SAT Solvers. AQTR Anzhela Yu. Matrosova, V. Provkin
2019	—	`conf`	Masking Internal Node Faults and Trojan Circuits in Logical Circuits. EWDTS Anzhela Yu. Matrosova, V. Provkin, Ekaterina Nikolaeva
2019	—	`conf`	Masking Robust Testable PDFs. EWDTS Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov
2018	C	`conf`	Finding False Paths for Sequential Circuits Using Operations on ROBDDs. IOLTS Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov
2018	J	`jnl`	Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh
2018	—	`conf`	Trojan circuits masking and debugging of combinational circuits with LUT insertion. AQTR Anzhela Yu. Matrosova, Sergey Ostanin
2017	—	`conf`	Detection and masking of Trojan Circuits in sequential logic. EWDTS Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergey Ostanin, Ekaterina Nikolaeva
2017	—	`conf`	Logic circuit design with gates, LUTs and MUXs oriented to mask faults. EWDTS Anzhela Yu. Matrosova, Sergey Ostanin, D. Tretyakov, Natalia Butorina
2017	—	`conf`	Preventing and masking Trojan circuits triggering out of working area. ECCTD Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko
2017	C	`conf`	Test pattern generation to detect multiple faults in ROBDD based combinational circuits. IOLTS Toral Shah, Anzhela Yu. Matrosova, Virendra Singh
2017	—	`conf`	Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh
2016	C	`conf`	A fault-tolerant sequential circuit design for SAFs and PDFs soft errors. IOLTS Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva
2016	—	`conf`	A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit. EWDTS Sergey Ostanin, Anzhela Yu. Matrosova, Natalia Butorina, V. Lavrov
2016	C	`conf`	A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
2016	—	`conf`	Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults. EWDTS Anzhela Yu. Matrosova, Eugeniy Mitrofanov
2016	—	`conf`	ROBDD based path delay fault testable combinational circuit synthesis. EWDTS Toral Shah, Virendra Singh, Anzhela Yu. Matrosova
2016	—	`conf`	ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself. EWDTS Anzhela Yu. Matrosova, Valentina Andreeva, Alexey Melnikov
2015	—	`conf`	A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
2015	—	`conf`	Fault-tolerant high performance scheme design. EWDTS Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva
2015	—	`conf`	Fully delay and multiple stuck-at faults testable FSM design. EWDTS Anzhela Yu. Matrosova, Valentina Andreeva, V. Tomkov
2015	C	`conf`	Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit. DDECS Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko
2015	—	`conf`	Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits. EWDTS Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah
2015	—	`conf`	PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. VDAT Toral Shah, Anzhela Yu. Matrosova, Virendra Singh
2015	J	`jnl`	Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits. Autom. Remote. Control. Anzhela Yu. Matrosova, Valeriy B. Lipskii
2015	C	`conf`	Simplification of fully delay testable combinational circuits. IOLTS Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah
2014	—	`conf`	Combinational circuits without false paths. EWDTS Anzhela Yu. Matrosova, Dmitry Kudin, Ekaterina Nikolaeva
2014	—	`conf`	Combinational part structure simplification of fully delay testable sequential circuit. EWDTS Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Elena Roumjantseva
2014	—	`conf`	Partially programmable circuit design. EWDTS Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Virendra Singh
2013	—	`conf`	Delay testable sequential circuit designs. EWDTS Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Virendra Singh
2013	J	`jnl`	Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. Autom. Remote. Control. Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh
2013	—	`conf`	Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. EWDTS Anzhela Yu. Matrosova, Sergey Ostanin, Alexey Melnikov, Virendra Singh
2013	—	`conf`	PDF testability of the circuits derived by special covering ROBDDs with gates. EWDTS Anzhela Yu. Matrosova, Ekaterina Nikolaeva, Dmitry Kudin, Virendra Singh
2011	—	`conf`	Selection of the state variables for partial enhanced scan techniques. EWDTS Anzhela Yu. Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh
2010	—	`conf`	Fault grading using Instruction-Execution graph. EWDTS K. R. Vinutha, Virendra Singh, Anzhela Yu. Matrosova, Manoj Singh Gaur
2010	—	`conf`	Path delay faults and ENF. EWDTS Anzhela Yu. Matrosova, Valeriy B. Lipsky, Alexey Melnikov, Virendra Singh
2003	C	`conf`	Designing FPGA based Self-Testing Checkers for m-out-of-n Codes. IOLTS Anzhela Yu. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. Nikitin
2002	—	`conf`	Survivable Discrete Circuits Design. IOLTW Anzhela Yu. Matrosova, Valentina Andreeva, Yu. Sedov
2001	—	`conf`	Survivable Self-Checking Sequential Circuits. DFT Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin
2001	—	`conf`	Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation. IOLTW Anzhela Yu. Matrosova, K. Nikitin, Olga Goloubeva
2000	—	`conf`	Self-Checking FSM Design with Observing only FSM Outputs. IOLTW Anzhela Yu. Matrosova, Sergey Ostanin
2000	J	`jnl`	Self-checking Synchronous FSM Network Design with Low Overhead. VLSI Design Anzhela Yu. Matrosova, Ilya Levin, Sergey Ostanin