Anup P. Jose - RankMe

13 papers Misc 1Journal 5Unranked 7

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. VLSI Technology and Circuits Mohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang, Ahmed E. AbdelRahman, Mahmoud A. Khalil, Anup P. Jose, Pavan Kumar Hanumolu
2022	J	`jnl`	A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process. IEEE J. Solid State Circuits Tianyu Wang, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu
2019	—	`conf`	A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. CICC Anup P. Jose, Valentin Abramzon, Mohamed Elzeftawi, Michael Wang, Kyunglok Kim, Younghoon Song, Shiva Moballegh, Jalil Kamali, Amir Amirkhany
2015	—	`conf`	3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. ISSCC Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang
2015	J	`jnl`	A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. IEEE J. Solid State Circuits Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang
2014	—	`conf`	Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. CICC Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang
2013	J	`jnl`	A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. IEEE J. Solid State Circuits Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang
2007	J	`jnl`	Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication. IEEE J. Solid State Circuits Anup P. Jose, Kenneth L. Shepard
2006	—	`conf`	Distributed Loss Compensation for Low-latency On-chip Interconnects. ISSCC Anup P. Jose, Kenneth L. Shepard
2006	J	`jnl`	Pulsed current-mode signaling for nearly speed-of-light intrachip communication. IEEE J. Solid State Circuits Anup P. Jose, George Patounakis, Kenneth L. Shepard
2005	—	`conf`	An on-chip jitter measurement circuit with sub-picosecond resolution. ESSCIRC Keith A. Jenkins, Anup P. Jose, David F. Heidel
2005	Misc	`conf`	On-Chip Spectrum Analyzer for Analog Built-In Self Test. VTS Anup P. Jose, Keith A. Jenkins, Scott K. Reynolds
2003	—	`conf`	Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. ASYNC Yee William Li, George Patounakis, Anup P. Jose, Kenneth L. Shepard, Steven M. Nowick