Anup Dandapat

30 papers Misc 1Journal 25Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
Achieving superior segmented CAM efficiency with pre-charge free local search based hybrid matcher for high speed applications.
Integr.
Shyamosree Goswami, Adwait Wakankar, Partha Bhattacharyya, Anup Dandapat
2024 J jnl
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine.
Integr.
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
2023 J jnl
SMS-CAM: Shared matchline scheme for content addressable memory.
Integr.
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
2022 J jnl
Design of a 1.29-1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoMT) for GPS and Satellite Navigation.
J. Circuits Syst. Comput.
Keshab Das, Anup Dandapat, Sanjay Kumar Jana
2021 J jnl
Match-line control unit for power and delay reduction in hybrid CAM.
IET Circuits Devices Syst.
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
2020 J jnl
A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM).
J. Inf. Sci. Eng.
Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat
2020 J jnl
Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat
2020 J jnl
Low-power content addressable memory design using two-layer P-N match-line control and sensing.
Integr.
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
2020 J jnl
The analogy of matchline sensing techniques for content addressable memory (CAM).
IET Comput. Digit. Tech.
Sandeep Mishra, Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Anup Dandapat
2019 — conf
A Low-Power Split-Controlled Single Ended Storage Content Addressable Memory.
iSES
Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat
2019 J jnl
Low discharge precharge free matchline structure for energy-efficient search using CAM.
Integr.
Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat
2018 J jnl
A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sandeep Mishra, Telajala Venkata Mahendra, Jyotishman Saikia, Anup Dandapat
2018 J jnl
Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory.
IEEE Trans. Consumer Electron.
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
2017 Misc conf
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.
VLSID
Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat
2017 J jnl
Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage.
IEEE Trans. Circuits Syst. II Express Briefs
Sandeep Mishra, Anup Dandapat
2017 J jnl
Self-Controlled High-Performance Precharge-Free Content-Addressable Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
2016 J jnl
A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sandeep Mishra, Telajala Venkata Mahendra, Anup Dandapat
2016 J jnl
A Novel Methodology for Design of Cyclic Combinational Circuits.
J. Low Power Electron.
Vinay Kumar, Chandan Kumar Jha, Gaurav Thapa, Anup Dandapat
2016 J jnl
Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique.
J. Circuits Syst. Comput.
Vinay Kumar, Anup Dandapat
2016 J jnl
EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control.
IEEE Trans. Very Large Scale Integr. Syst.
Sandeep Mishra, Anup Dandapat
2015 J jnl
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit.
IEEE Trans. Very Large Scale Integr. Syst.
Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar, Anup Dandapat
2014 J jnl
Design of 64-Bit Squarer Based on Vedic Mathematics.
J. Circuits Syst. Comput.
Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat
2014 J jnl
Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique.
J. Signal Process. Syst.
D. Kayal, Posiba Mostafa, Anup Dandapat, Chandan Kumar Sarkar
2014 J jnl
Improved matrix multiplier design for high-speed digital signal processing applications.
IET Circuits Devices Syst.
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
2013 J jnl
A Novel Design of Seven Segment Decoder Using Cyclic Combinational Technique.
J. Low Power Electron.
D. Ghosh, P. C. Mondal, D. Kayal, Partha Bhattacharyya, Anup Dandapat
2013 — conf
Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications.
ISED
Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat
2012 — conf
Design of High Speed Vedic Multiplier for Decimal Number System.
VDAT
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
2011 J jnl
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics.
Microelectron. J.
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
2011 — conf
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications.
ISED
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
2008 J jnl
Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM.
J. Low Power Electron.
Anup Dandapat, D. Kayal, D. Mukhopadhyay