Anuja Sehgal

19 papers A* 1A 9C 1Journal 7Unranked 1
YearRankTypeTitle / Venue / Authors
2009 J jnl
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing.
IEEE Des. Test Comput.
Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
2009 A conf
Test access mechanism for multiple identical cores.
ITC
Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield
2009 J jnl
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.
IEEE Trans. Computers
Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty
2008 J jnl
Power-aware SoC test planning for effective utilization of port-scalable testers.
ACM Trans. Design Autom. Electr. Syst.
Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty
2008 A conf
Test Access Mechanism for Multiple Identical Cores.
ITC
Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield
2007 J jnl
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs.
IEEE Trans. Computers
Anuja Sehgal, Krishnendu Chakrabarty
2007 J jnl
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
CoRR
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
2007 A conf
Test cost reduction for the AMD™ Athlon processor using test partitioning.
ITC
Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
2006 A conf
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.
DATE
Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2006 J jnl
Test infrastructure design for mixed-signal SOCs with wrapped analog cores.
IEEE Trans. Very Large Scale Integr. Syst.
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
2005 C conf
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs.
ICCD
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
2005 A conf
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores.
DATE
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
2005 A conf
Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs.
ICCAD
Anuja Sehgal, Krishnendu Chakrabarty
2004 A conf
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures.
DATE
Anuja Sehgal, Krishnendu Chakrabarty
2004 A conf
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.
ITC
Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2004 J jnl
SOC test planning using virtual test access architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
2003 A conf
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers.
ICCAD
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
2003 A* conf
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.
DAC
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty
2003 — conf
Yield analysis for repairable embedded memories.
ETW
Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty