António Canelas

36 papers A 3B 1C 3Journal 16Unranked 13

Year	Rank	Type	Title / Venue / Authors
2022	C	`conf`	A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications. ISCAS Fábio Passos, Rafael Vieira, António Canelas, Ricardo Póvoa, Nuno Lourenço, Nuno Horta, Jorge Guilherme
2021	J	`jnl`	Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2020	J	`jnl`	A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications. IEEE Trans. Circuits Syst. II Express Briefs Ricardo Póvoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes
2020	J	`jnl`	A new family of CMOS inverter-based OTAs for biomedical and healthcare applications. Integr. Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes
2020	J	`jnl`	FUZYE: A Fuzzy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. António Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Lourenço, Jorge Guilherme, João Paulo Carvalho, Nuno Horta
2020	J	`jnl`	Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications. Microelectron. J. Ricardo Póvoa, Richa Arya, António Canelas, Fábio Passos, Ricardo Martins, Nuno Lourenço, Nuno Horta
2019	—	`conf`	A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers. SMACD Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes
2019	—	`conf`	Artificial Neural Networks as an Alternative for Automatic Analog IC Placement. SMACD Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins
2019	—	`conf`	Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization. SMACD Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Póvoa, Nuno Horta, Emmanuel Moutaye
2019	J	`jnl`	Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
2019	—	`conf`	Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing. SMACD Nuno Lourenço, Engin Afacan, Ricardo Martins, Fábio Passos, António Canelas, Ricardo Póvoa, Nuno Horta, Günhan Dündar
2018	—	`conf`	A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. SMACD António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta
2018	J	`jnl`	Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. Integr. Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2018	—	`conf`	Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. SMACD Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández
2018	—	`conf`	On the Exploration of Promising Analog IC Designs via Artificial Neural Networks. SMACD Nuno Lourenço, Joao Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta
2018	J	`jnl`	Parallel SAX/GA for financial pattern matching using NVIDIA's GPU. Expert Syst. Appl. João Baúto, António Canelas, Rui Ferreira Neves, Nuno Horta
2018	J	`jnl`	Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement. IEEE Trans. Circuits Syst. II Express Briefs Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Cavaco Gomes Horta, João Goes
2018	J	`jnl`	Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving. IEEE Trans. Circuits Syst. II Express Briefs Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes
2017	A	`conf`	Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing. DATE António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
2017	—	`conf`	Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. SMACD Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017	—	`conf`	New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. SMACD Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017	J	`jnl`	Stochastic-based placement template generator for analog IC layout-aware synthesis. Integr. Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2017	—	`conf`	Systematic design of a voltage controlled oscillator using a layout-aware approach. SMACD Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta
2016	J	`jnl`	AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. Integr. Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta
2016	J	`jnl`	Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer. Integr. Mrinalinee Pandey, António Canelas, Ricardo Póvoa, Jorge Alves Torres, João Costa Freire, Nuno Lourenço, Nuno Horta
2016	—	`conf`	On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies. SMACD Ricardo Martins, António Canelas, Nuno Lourenço, Nuno Horta
2016	—	`conf`	Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations. SMACD António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
2015	C	`conf`	Extraction and application of wiring symmetry rules to route analog multiport terminals. ISCAS Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2015	J	`jnl`	Floorplan-aware analog IC sizing and optimization based on topological constraints. Integr. Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta
2014	J	`jnl`	Electromigration-aware analog Router with multilayer multiport terminal structures. Integr. Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2014	A	`conf`	Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures. DATE Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2014	C	`conf`	LC-VCO automatic synthesis using multi-objective evolutionary techniques. ISCAS Ricardo Povoa, Ricardo Lourenco, Nuno Lourenço, António Canelas, Ricardo Martins, Nuno Horta
2013	J	`jnl`	A SAX-GA approach to evolve investment strategies on financial markets based on pattern discovery techniques. Expert Syst. Appl. António Canelas, Rui Ferreira Neves, Nuno Horta
2013	—	`conf`	Multi-dimensional pattern discovery in financial time series using sax-ga with extended robustness. GECCO (Companion) António Canelas, Rui Ferreira Neves, Nuno Horta
2013	B	`conf`	Multi-port multi-terminal analog router based on an evolutionary optimization kernel. IEEE Congress on Evolutionary Computation Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2012	A	`conf`	A new SAX-GA methodology applied to investment strategies optimization. GECCO António Canelas, Rui Ferreira Neves, Nuno Horta