Antonios Thanailakis

24 papers A 3C 1Journal 11Unranked 9

Year	Rank	Type	Title / Venue / Authors
2010	J	`jnl`	A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures. J. Circuits Syst. Comput. Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
2008	J	`jnl`	Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays. J. Low Power Electron. Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
2007	J	`jnl`	A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck CoRR Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
2007	—	`conf`	Designing Heterogeneous FPGAs with Multiple SBs. ARC Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis
2007	J	`jnl`	Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. J. Syst. Archit. Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
2006	A	`conf`	A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis
2006	J	`jnl`	Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. J. VLSI Signal Process. Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis
2006	—	`conf`	Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. PATMOS Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
2006	A	`conf`	Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. DATE Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
2006	C	`conf`	Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. VLSI-SoC Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
2006	J	`jnl`	Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. Comput. Commun. Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
2005	A	`conf`	A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. DATE Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
2005	—	`conf`	A Modified Spiral Search Algorithm and its Embedded Hardware Implementation. IEC (Prague) Nikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Antonios Thanailakis
2005	J	`jnl`	A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Trans. Inf. Syst. Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos
2005	—	`conf`	Improving the Memory Bandwidth Utilization Using Loop Transformations. PATMOS Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
2005	—	`conf`	Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. WWIC Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis
2004	—	`conf`	A reusable IP FFT core for DSP applications. ISCAS (3) Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis
2004	J	`jnl`	Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate. Microelectron. J. Ioannis Tsimperidis, Ioannis Karafyllidis, Antonios Thanailakis
2004	—	`conf`	Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. WWIC Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis
2004	—	`conf`	Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. SAMOS Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
2003	J	`jnl`	Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. Real Time Imaging Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis
2001	—	`conf`	Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis
1996	J	`jnl`	A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation. Integr. Panagiotis Tzionas, Antonios Thanailakis, Philippos Tsalides
1993	J	`jnl`	2-Dimensional minimum cost path planning using a cellular automaton architecture. Integr. Panagiotis Tzionas, Philippos Tsalides, Antonios Thanailakis