Antonio Pullini

54 papers A* 2A 6C 6Journal 20Unranked 20

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	—	`conf`	4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021	A	`conf`	MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. DATE Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
2021	J	`jnl`	Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2020	J	`jnl`	MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. CoRR Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
2020	J	`jnl`	Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI. CoRR Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2020	J	`jnl`	Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI. Integr. Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2019	C	`conf`	An Energy Efficient System for Touch Modality Classification in Electronic Skin Applications. ISCAS Mario Osta, Ali Ibrahim, Michele Magno, Manuel Eggimann, Antonio Pullini, Paolo Gastaldo, Maurizio Valle
2019	J	`jnl`	Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE J. Solid State Circuits Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini
2018	J	`jnl`	A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
2018	J	`jnl`	An Energy Efficient E-Skin Embedded System for Real-Time Tactile Data Decoding. J. Low Power Electron. Michele Magno, Ali Ibrahim, Antonio Pullini, Maurizio Valle, Luca Benini
2018	—	`conf`	GAP-8: A RISC-V SoC for AI at the Edge of the IoT. ASAP Eric Flamand, Davide Rossi, Francesco Conti, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini
2018	C	`conf`	Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. ISCAS Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2018	—	`conf`	Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. ESSCIRC Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini
2017	J	`jnl`	A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse
2017	J	`jnl`	An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. Circuits Syst. I Regul. Pap. Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2017	—	`conf`	Energy Efficient System for Tactile Data Decoding Using an Ultra-Low Power Parallel Platform. NGCAS Michele Magno, Ali Ibrahim, Antonio Pullini, Maurizio Valle, Luca Benini
2017	J	`jnl`	Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
2017	J	`jnl`	Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. Very Large Scale Integr. Syst. Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
2017	—	`conf`	Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. PATMOS Pasquale Davide Schiavone, Francesco Conti, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand, Luca Benini
2017	—	`conf`	Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology. PATMOS Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
2017	—	`conf`	μDMA: An autonomous I/O subsystem for IoT end-nodes. PATMOS Antonio Pullini, Davide Rossi, Germain Haugou, Luca Benini
2016	—	`conf`	193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
2016	—	`conf`	A Dual Processor Energy-Efficient Platform with Multi-core Accelerator for Smart Sensing. S-CUBE Antonio Pullini, Stefan Mach, Michele Magno, Luca Benini
2016	C	`conf`	A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. ISCAS Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
2016	J	`jnl`	A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini
2016	J	`jnl`	An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
2016	J	`jnl`	PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision. J. Signal Process. Syst. Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
2015	A*	`conf`	Exploring architectural heterogeneity in intelligent vision systems. HPCA Nandhini Chandramoorthy, Giuseppe Tagliavini, Kevin M. Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini
2015	—	`conf`	PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini
2015	C	`conf`	Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores. VLSI-SoC Michael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta
2014	—	`conf`	A lightweight cryptographic system for implantable biosensors. BioCAS Sara S. Ghoreishizadeh, Tolga Yalçin, Antonio Pullini, Giovanni De Micheli, Wayne P. Burleson, Sandro Carrara
2014	—	`conf`	Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform. CVPR Workshops Francesco Conti, Antonio Pullini, Luca Benini
2014	—	`conf`	Energy-efficient vision on the PULP platform for ultra-low power parallel computing. SiPS Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini
2014	—	`conf`	Sub-mW reconfigurable interface IC for electrochemical sensing. BioCAS Sara S. Ghoreishizadeh, Cristina Boero, Antonio Pullini, Camilla Baj-Rossi, Sandro Carrara, Giovanni De Micheli
2012	J	`jnl`	Row-based FBB: A design-time optimization for post-silicon tunable circuits. Microelectron. J. Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini
2011	J	`jnl`	Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
2010	C	`conf`	3D NoCs - Unifying inter & intra chip communication. ISCAS Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini
2010	A	`conf`	Automatic synthesis of near-threshold circuits with fine-grained performance tunability. ISLPED Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini
2010	A*	`conf`	Networks on Chips: from research to products. DAC Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini
2009	—	`conf`	A floorplan-aware interactive tool flow for NoC design and synthesis. SoCC Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini
2009	A	`conf`	Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. DATE Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli
2009	A	`conf`	Physically clustered forward body biasing for variability compensation in nanometer CMOS design. DATE Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii
2008	A	`conf`	A Scalable Algorithmic Framework for Row-Based Power-Gating. DATE Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2008	J	`jnl`	Network-on-Chip design and synthesis outlook. Integr. David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli
2008	C	`conf`	On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2008	—	`conf`	Optimal sleep transistor synthesis under timing and area constraints. ACM Great Lakes Symposium on VLSI Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2007	J	`jnl`	Bringing NoCs to 65 nm. IEEE Micro Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini
2007	—	`conf`	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2007	—	`conf`	NoC Design and Implementation in 65nm Technology. NOCS Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
2007	J	`jnl`	Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli
2007	A	`conf`	Timing-driven row-based power gating. ISLPED Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2006	—	`conf`	Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. SoC Srinivasan Murali, Rutuparna Tamhankar, Federico Angiolini, Antonio Pullini, David Atienza, Luca Benini, Giovanni De Micheli
2005	—	`conf`	Fault tolerance overhead in network-on-chip flow control schemes. SBCCI Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini