Antonio Mastrandrea

51 papers B 2C 2Journal 17Unranked 30

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. CoRR Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2025	J	`jnl`	Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. ACM Trans. Embed. Comput. Syst. Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2025	—	`conf`	Fast FPGA-Based Implementation of the QP-Dyn Stream Cipher using High-Level Synthesis. HPEC Paolo Palazzari, Luigi Accardi, Antonio Mastrandrea, Pasquale Tommasino, Alessandro Trifiletti
2025	B	`conf`	HD-CBBIN: A Lightweight Approach for Contextual Bandit Learning in Real-Time Applications. IJCNN Marco Angioli, Antonello Rosato, Marcello Barbirotta, Rocco Martino, Andrea Marcelli, Antonio Mastrandrea, Mauro Olivieri
2025	—	`conf`	Implementing the RISC-V Debug Specification on an Interleaved Multi-Threading Core. ApplePies Andrea Marcelli, Marco Pisani, Marco Angioli, Rocco Martino, Antonio Mastrandrea, Mauro Olivieri
2024	J	`jnl`	A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection. IEEE Access Francesco Vigli, Marcello Barbirotta, Abdallah Cheikh, Francesco Menichelli, Antonio Mastrandrea, Mauro Olivieri
2024	J	`jnl`	A Simple Microwave Imaging System for Food Product Inspection through a Symmetry-Based Microwave Imaging Approach. Sensors Gennaro Bellizzi, Alessio Buzzin, Lorenzo Crocco, Antonio Mastrandrea, Noemi Zeni, Sabrina Zumbo, Marta Cavagnaro
2024	B	`conf`	AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs. IJCNN Marco Angioli, Saeid Jamili, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Antonello Rosato, Mauro Olivieri
2024	—	`conf`	Alternative Implementations of Error Correcting Codes in Register Files of a RISC-V Safety Critical Processor. ApplePies Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Francesco Menichelli, Mauro Olivieri
2024	J	`jnl`	Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. IEEE Trans. Computers Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
2024	—	`conf`	Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation. DFT Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri
2024	J	`jnl`	Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. IEEE Access Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
2024	—	`conf`	Exploring Variable Latency Dividers in Vector Hardware Accelerators. PRIME Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri
2024	—	`conf`	Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor. DFT Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri
2023	—	`conf`	A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. ApplePies Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
2023	—	`conf`	Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor. PRIME Marco Angioli, Marcello Barbirotta, Antonio Mastrandrea, Saeid Jamili, Mauro Olivieri
2023	—	`conf`	Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. ApplePies Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri
2023	—	`conf`	Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. ApplePies Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri
2022	—	`conf`	3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool. AISEM Silvia Casalinuovo, Alessio Buzzin, Antonio Mastrandrea, Ivan Mazzetta, Marcello Barbirotta, Lorenzo Iannascoli, Augusto Nascetti, Giampiero de Cesare, Donatella Puglisi, Domenico Caputo
2022	—	`conf`	Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. PRIME Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2022	—	`conf`	Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. ApplePies Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri
2022	J	`jnl`	Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. IEEE Access Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2022	—	`conf`	Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ApplePies Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri
2021	—	`conf`	A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. DFT Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri
2021	—	`conf`	A Ladder Network Theoretical Approach for the Automatic Monitoring of Distributed Sensors. AISEM Alessandro Zompanti, Anna Sabatini, Simone Grasso, Giorgio Pennazza, Antonio Mastrandrea, Giuseppe Ferri, Gianluca Barile, Marco Santonico
2021	J	`jnl`	Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. IEEE Micro Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
2021	J	`jnl`	SystemC Implementation of Stochastic Petri Nets for Simulation and Parameterization of Biological Networks. ACM Trans. Embed. Comput. Syst. Nicola Bombieri, Silvia Scaffeo, Antonio Mastrandrea, Simone Caligola, Tommaso Carlucci, Franco Fummi, Carlo Laudanna, Gabriela Constantin, Rosalba Giugno
2020	—	`conf`	Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. DFT Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri
2020	J	`jnl`	Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. CoRR Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri
2019	—	`conf`	A PULP-based Parallel Power Controller for Future Exascale Systems. ICECS Andrea Bartolini, Davide Rossi, Antonio Mastrandrea, Christian Conficoni, Simone Benatti, Andrea Tilli, Luca Benini
2019	—	`conf`	A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. ApplePies Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2019	—	`conf`	Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. ApplePies Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2019	J	`jnl`	Full System Emulation of Approximate Memory Platforms with AppropinQuo. J. Low Power Electron. Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2019	—	`conf`	On the Simulation and Automatic Parametrization of Metabolic Networks Through Electronic Design Automation. CIBB Nicola Bombieri, Antonio Mastrandrea, Silvia Scaffeo, Simone Caligola, Franco Fummi, Carlo Laudanna, Gabriela Constantin, Rosalba Giugno
2019	—	`conf`	Quality Aware Approximate Memory in RISC-V Linux Kernel. PRIME Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2019	—	`conf`	Quality Aware Selective ECC for Approximate DRAM. ApplePies Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018	—	`conf`	AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. NGCAS Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018	—	`conf`	Approximate Memory Support for Linux Early Allocators in ARM Architectures. ApplePies Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018	C	`conf`	Characterizing noise pulse effects on the power consumption of idle digital cells. ISCAS Mauro Olivieri, Usman Khalid, Antonio Mastrandrea, Francesco Menichelli
2018	—	`conf`	Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder. ISC Workshops Giulia Stazi, Lorenzo Adani, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2018	—	`conf`	Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. ApplePies Giulia Stazi, Federica Silvestri, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli
2017	J	`jnl`	Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops. CoRR Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
2017	—	`conf`	Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. NGCAS Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli
2017	—	`conf`	The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. ApplePies Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2017	J	`jnl`	The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. CoRR Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2016	—	`conf`	An Emulator for Approximate Memory Platforms Based on QEmu. ApplePies Francesco Menichelli, Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri
2015	J	`jnl`	Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. Microelectron. Reliab. Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
2014	J	`jnl`	A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. Zia Abbas, Antonio Mastrandrea, Mauro Olivieri
2014	C	`conf`	Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. DSD Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
2014	J	`jnl`	Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. Mauro Olivieri, Antonio Mastrandrea
2013	J	`jnl`	A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. VLSI Design Mauro Olivieri, Antonio Mastrandrea