Antonio Liscidini

68 papers C 2Journal 36Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Gain and Nonlinearity Analysis in Quantized-Analog Amplifiers Using Fourier Transform. IEEE Trans. Circuits Syst. I Regul. Pap. Parsa Tahbazalli, Antonio Liscidini
2025	J	`jnl`	Guest Editorial Special Issue on the 2025 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs Antonio Liscidini
2025	J	`jnl`	Guest Editorial Special Issue on the 2025 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs Antonio Liscidini
2024	—	`conf`	4.5 A Reconfigurable, Multi-Channel Quantized-Analog Transmitter with <-35dB EVM and <-51dBc ACLR in 22nm FDSOI. ISSCC John Zhong, Konstantinos Vasilakopoulos, Antonio Liscidini
2024	J	`jnl`	DC-Coupled Biasing Technique for Quantized-Analog Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs Armin Choopani, Antonio Liscidini
2024	J	`jnl`	Guest Editorial Special Issue on the 2024 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs Edoardo Bonizzoni, Sebastian Hoyos, Antonio Liscidini
2024	J	`jnl`	Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs Antonio Liscidini
2023	—	`conf`	A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency. ESSCIRC Tianwen Tang, Antonio Liscidini
2023	C	`conf`	A 36 GHz Bandwidth, High Linear, Low Power, Driver Modulator, in 28 nm CMOS Technology Based on Quantized-Analog Signal Processing. ISCAS Xhulio Selmani, Gurjeet Singh, Rinaldo Castello, Antonio Liscidini
2023	—	`conf`	A Wide Bandwidth, Low Power, Linear Quantized-Analog VGA in 28 nm CMOS Technology and 1.2V Supply. PRIME Gurjeet Singh, Xhulio Selmani, Rinaldo Castello, Antonio Liscidini
2022	—	`conf`	A 2GHz voltage mode power scalable RF-Front-End with 2.5dB-NF and 0.5dBm-1dBCP. CICC Justin Yonghui Kim, Antonio Liscidini
2022	J	`jnl`	Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law. IEEE Open J. Circuits Syst. Qingnan Yu, Tony Chan Carusone, Antonio Liscidini
2021	J	`jnl`	A 2.4-GHz 1.3-mW OQPSK RF Front-End TX Based on an Injection-Locked Power Amplifier. IEEE J. Solid State Circuits Saba Zargham, Zexi Ji, Antonio Liscidini
2020	J	`jnl`	Temperature Compensation of Crystal References in NB-IoT Modems. IEEE Trans. Circuits Syst. I Regul. Pap. Tuomas Haapala, Antonio Liscidini, Kari A. I. Halonen
2019	J	`jnl`	A Quantized Analog RF Front End. IEEE J. Solid State Circuits Javid Musayev, Antonio Liscidini
2019	J	`jnl`	A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach. IEEE Trans. Circuits Syst. I Regul. Pap. Sevil Zeynep Lulec, David A. Johns, Antonio Liscidini
2018	J	`jnl`	A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers. IEEE J. Solid State Circuits QiWei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone
2018	—	`conf`	A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance. CICC Zhonghong Jiang, David A. Johns, Antonio Liscidini
2018	—	`conf`	Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier. ESSCIRC Zexi Ji, Saba Zargham, Antonio Liscidini
2018	—	`conf`	Quantized Analog RX Front-End for SAW-Less Applications. ESSCIRC Javid Musayev, Antonio Liscidini
2017	—	`conf`	A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS. CICC QiWei Wang, Hajime Shibata, Anthony Chan Carusone, Antonio Liscidini
2017	—	`conf`	F4: Wireless low-power transceivers for local and wide-area networks. ISSCC Jan van Sinderen, Danielle Griffith, Ken Yamamoto, Antonio Liscidini, Young-sub Yuk
2017	—	`conf`	Filtering ADCs for wireless receivers: A survey. MWSCAS QiWei Wang, Antonio Liscidini, Anthony Chan Carusone
2016	—	`conf`	20.9 A 1.92mW filtering transimpedance amplifier for RF current passive mixers. ISSCC Tian Ya Liu, Antonio Liscidini
2016	J	`jnl`	A Simplified Model for Passive-Switched-Capacitor Filters With Complex Poles. IEEE Trans. Circuits Syst. II Express Briefs Sevil Zeynep Lulec, David A. Johns, Antonio Liscidini
2016	J	`jnl`	Class-C PA-VCO Cell for FSK and GFSK Transmitters. IEEE J. Solid State Circuits Chuanwei Li, Antonio Liscidini
2016	J	`jnl`	Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Edgar Sánchez-Sinencio, Jan Mulder, Antonio Liscidini, Eric A. M. Klumperink, Elad Alon
2015	—	`conf`	13.6 A 600μW Bluetooth low-energy front-end receiver in 0.13μm CMOS technology. ISSCC Anith Selvakumar, Meysam Zargham, Antonio Liscidini
2015	—	`conf`	A current re-use PA-VCO cell for low-power BLE transmitters. ESSCIRC Chuanwei Li, Antonio Liscidini
2015	C	`conf`	Bluetooth low energy receiver system design. ISCAS Alessandra Pipino, Antonio Liscidini, Karen Wan, Andrea Baschirotto
2015	J	`jnl`	Current-Recycling Complex Filter for Bluetooth-Low-Energy Applications. IEEE Trans. Circuits Syst. II Express Briefs Anith Selvakumar, Antonio Liscidini
2015	J	`jnl`	Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications. IEEE J. Solid State Circuits Anith Selvakumar, Meysam Zargham, Antonio Liscidini
2014	J	`jnl`	A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer. IEEE J. Solid State Circuits Nicola Codega, Paolo Rossi, Alberto Pirola, Antonio Liscidini, Rinaldo Castello
2014	J	`jnl`	A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers. IEEE J. Solid State Circuits Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello
2014	J	`jnl`	An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators. IEEE J. Solid State Circuits Marco Garampazzi, Stefano Dal Toso, Antonio Liscidini, Danilo Manstretta, P. Mendez, Luca Romanò, Rinaldo Castello
2013	—	`conf`	A low out-of-band noise LTE transmitter with current-mode approach. ESSCIRC Nicola Codega, Antonio Liscidini, Rinaldo Castello
2013	J	`jnl`	An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory. IEEE Trans. Circuits Syst. II Express Briefs Marco Sosio, Antonio Liscidini, Rinaldo Castello
2013	—	`conf`	An LTE transmitter using a class-A/B power mixer. ISSCC Paolo Rossi, Nicola Codega, Danilo Gerna, Antonio Liscidini, Daniele Ottini, Yong He, Alberto Pirola, Enrico Sacchi, Gregory Uehara, Chao Yang, Rinaldo Castello
2013	—	`conf`	F5: Frequency generation and clock distribution. ISSCC Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner
2013	J	`jnl`	Introduction to the Special Issue on the 38th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Antonio Liscidini, Douglas Smith
2013	J	`jnl`	SAW-Less Analog Front-End Receivers for TDD and FDD. IEEE J. Solid State Circuits Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello
2013	—	`conf`	SAW-less analog front-end receivers for TDD and FDD. ISSCC Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello
2012	J	`jnl`	A 2G/3G Cellular Analog Baseband Based on a Filtering ADC. IEEE Trans. Circuits Syst. II Express Briefs Marco Sosio, Antonio Liscidini, Rinaldo Castello
2012	J	`jnl`	A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps. IEEE J. Solid State Circuits Ping Lu, Antonio Liscidini, Pietro Andreani
2012	—	`conf`	A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers. ISSCC Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello
2012	—	`conf`	A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO. ISSCC Luca Fanori, Antonio Liscidini, Pietro Andreani
2012	—	`conf`	A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter. NORCHIP Ping Lu, Pietro Andreani, Antonio Liscidini
2012	J	`jnl`	A Dither-Less All Digital PLL for Cellular Transmitters. IEEE J. Solid State Circuits Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello
2012	J	`jnl`	Clock/Frequency Generation Circuits and Systems. J. Electr. Comput. Eng. Woogeun Rhee, Antonio Liscidini, Jae-Yoon Sim, Kenichi Okada, Sudhakar Pamarti
2011	—	`conf`	A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs. ESSCIRC Ping Lu, Pietro Andreani, Antonio Liscidini
2011	—	`conf`	A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC. ESSCIRC Marco Sosio, Antonio Liscidini, Rinaldo Castello, Fernando De Bernardinis
2011	—	`conf`	A dither-less all digital PLL for cellular transmitters. CICC Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello
2011	J	`jnl`	Corrections to "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping" [Sep 10 1770-1780]. IEEE J. Solid State Circuits Alberto Pirola, Antonio Liscidini, Rinaldo Castello
2010	—	`conf`	3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL. ISSCC Luca Fanori, Antonio Liscidini, Rinaldo Castello
2010	J	`jnl`	Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning. IEEE J. Solid State Circuits Luca Fanori, Antonio Liscidini, Rinaldo Castello
2010	J	`jnl`	Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping. IEEE J. Solid State Circuits Alberto Pirola, Antonio Liscidini, Rinaldo Castello
2010	J	`jnl`	Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications. IEEE J. Solid State Circuits Marika Tedeschi, Antonio Liscidini, Rinaldo Castello
2010	J	`jnl`	Two-Dimensions Vernier Time-to-Digital Converter. IEEE J. Solid State Circuits Luca Vercesi, Antonio Liscidini, Rinaldo Castello
2009	—	`conf`	A 1.25mW 75dB-SFDR CT filter with in-band noise reduction. ISSCC Antonio Liscidini, Alberto Pirola, Rinaldo Castello
2009	—	`conf`	Time to digital converter based on a 2-dimensions Vernier architecture. CICC Antonio Liscidini, Luca Vercesi, Rinaldo Castello
2008	—	`conf`	A 0.23mm2 free coil ZigBee receiver based on a bond-wire self-oscillating mixer. ESSCIRC Marika Tedeschi, Antonio Liscidini, Rinaldo Castello
2008	—	`conf`	A 2.4 GHz 3.6mW 0.35mm ISSCC Antonio Liscidini, Marika Tedeschi, Rinaldo Castello
2008	J	`jnl`	Analysis and Design of Configurable LNAs in Feedback Common-Gate Topologies. IEEE Trans. Circuits Syst. II Express Briefs Antonio Liscidini, Giuseppe Martini, Daniele Mastantuono, Rinaldo Castello
2006	J	`jnl`	A 0.13 μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. IEEE J. Solid State Circuits Antonio Liscidini, Massimo Brandolini, Davide Sanzogni, Rinaldo Castello
2006	—	`conf`	A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO. ISSCC Antonio Liscidini, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello
2006	—	`conf`	Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End. CICC Antonio Liscidini, Cesare Ghezzi, Emanuele Depaoli, Guido Albasini, Ivan Bietti, Rinaldo Castello
2006	J	`jnl`	Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell. IEEE J. Solid State Circuits Antonio Liscidini, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello
2005	J	`jnl`	A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications. IEEE J. Solid State Circuits Paolo Rossi, Antonio Liscidini, Massimo Brandolini, Francesco Svelto