Antonio J. Acosta

56 papers A 3C 9Misc 1Journal 16Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Low Entropy Masking Protection Scheme for Ascon Cipher to Counteract Side-Channel Attacks. DCIS Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Miguel Martín-González, Alejandro Casado-Galán, Antonio J. Acosta
2025	—	`conf`	TERORO - Transient Effect Ring Oscillator and Ring Oscillator Configurable Hybrid PUF. SMACD Alejandro Casado-Galán, J. Núñez-Martínez, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta
2024	C	`conf`	Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher. DSD Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Virginia Zúñiga-González, Antonio J. Acosta
2024	—	`conf`	Electromagnetic Fault Injection Attack Methodology against AES Hardware Implementation. DCIS Alejandro Casado-Galán, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta, Erica Tena-Sánchez
2024	—	`conf`	Hardware implementations, SCA/FIA attacks, and countermeasures for the ASCON AEAD cipher: a review. DCIS Miguel Martín-González, Erica Tena-Sánchez, F. Eugenio Potestad Ordóñez, Antonio J. Acosta
2023	—	`conf`	A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks. DCIS Virginia Zúñiga-González, Erica Tena-Sánchez, Antonio J. Acosta
2022	J	`jnl`	Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. IEEE Access Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Antonio J. Acosta, Carlos Jesús Jiménez-Fernández, Ricardo Chaves
2022	J	`jnl`	Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embed. Syst. Lett. Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2021	J	`jnl`	Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices. IEEE Trans. Emerg. Top. Comput. Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2020	J	`jnl`	Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. ACM J. Emerg. Technol. Comput. Syst. Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2019	J	`jnl`	Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks. Int. J. Circuit Theory Appl. Erica Tena-Sánchez, Antonio J. Acosta
2018	—	`conf`	Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. DCIS Erica Tena-Sánchez, Ignacio M. Delgado-Lozano, Juan Núñez, Antonio J. Acosta
2018	—	`conf`	Effect of Temperature Variation in Experimental DPA and DEMA Attacks. PATMOS Erica Tena-Sánchez, Antonio J. Acosta
2017	J	`jnl`	Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview. Int. J. Circuit Theory Appl. Antonio J. Acosta, Tommaso Addabbo, Erica Tena-Sánchez
2017	J	`jnl`	Guest Editorial "Secure lightweight crypto-hardware". Int. J. Circuit Theory Appl. Antonio J. Acosta, Tommaso Addabbo
2017	J	`jnl`	Power and Energy Issues on Lightweight Cryptography. J. Low Power Electron. Antonio J. Acosta, Erica Tena-Sánchez, Carlos Jesús Jiménez-Fernández, Javier M. Mora-Merchan
2016	J	`jnl`	Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions. Int. J. Circuit Theory Appl. Piedad Brox, Macarena C. Martínez-Rodríguez, Erica Tena-Sánchez, Iluminada Baturone, Antonio J. Acosta
2016	—	`conf`	Secure cryptographic hardware implementation issues for high-performance applications. PATMOS Erica Tena-Sánchez, Antonio J. Acosta, Juan Núñez
2015	C	`conf`	DPA vulnerability analysis on Trivium stream cipher using an optimized power model. ISCAS Erica Tena-Sánchez, Antonio J. Acosta
2015	—	`conf`	Programmable ASICs for model predictive control. ICIT Macarena C. Martínez-Rodríguez, Piedad Brox, Erica Tena, Antonio J. Acosta, Iluminada Baturone
2014	J	`jnl`	A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta
2014	—	`conf`	Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. PATMOS Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta
2014	C	`conf`	Low-Power Differential Logic Gates for DPA Resistant Circuits. DSD Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta
2013	J	`jnl`	A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. IEEE Trans. Circuits Syst. I Regul. Pap. Piedad Brox, Javier Castro-Ramirez, Macarena C. Martínez-Rodríguez, Erica Tena, Carlos Jesús Jiménez-Fernández, Iluminada Baturone, Antonio J. Acosta
2012	—	`conf`	ASIC-in-the-loop methodology for verification of piecewise affine controllers. ICECS Macarena C. Martínez-Rodríguez, Piedad Brox, Javier Castro-Ramirez, Erica Tena, Antonio J. Acosta, Iluminada Baturone
2010	C	`conf`	Optimization of clock-gating structures for low-leakage high-performance applications. ISCAS Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta
2009	—	`conf`	Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. PATMOS Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta
2008	—	`conf`	A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. APCCAS Antonio Jose Ginés, Ricardo Doldán, Alberto Villegas, Antonio J. Acosta, Maria Angeles Jalón, Diego Vázquez, Adoración Rueda, Eduardo J. Peralías
2007	—	`conf`	A switching noise vision of the optimization techniques for low-power synthesis. ECCTD Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
2007	C	`conf`	Asymmetric clock driver for improved power and noise performances. ISCAS Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
2007	C	`conf`	Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications. ISCAS Renato Rimolo-Donadio, Antonio J. Acosta, Wolfgang H. Krautschneider
2006	—	`conf`	Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta
2005	J	`jnl`	A mixed-signal integrated circuit for FM-DCSK modulation. IEEE J. Solid State Circuits Manuel Delgado-Restituto, Antonio J. Acosta, Ángel Rodríguez-Vázquez
2005	J	`jnl`	Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero
2004	—	`conf`	A mixed-signal integrated circuit for FM-DCSK modulation. ESSCIRC Manuel Delgado-Restituto, Antonio J. Acosta, Ángel Rodríguez-Vázquez
2003	—	`conf`	A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta
2002	—	`conf`	A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta
2002	—	`ed.`	Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002 PATMOS Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
2002	—	`conf`	Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero
2001	A	`conf`	Analog/mixed-signal IP modeling for design reuse. DATE Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda
2001	—	`conf`	Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
2001	A	`conf`	HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
2000	A	`conf`	A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. DATE Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
2000	—	`conf`	An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. PATMOS Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda
2000	—	`conf`	Degradation Delay Model Extension to CMOS Gates. PATMOS Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
2000	C	`conf`	Inertial and degradation delay model for CMOS logic gates. ISCAS Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
2000	—	`conf`	Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero
2000	C	`conf`	VHDL-based behavioural description of pipeline ADCs. ISCAS Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
1999	J	`jnl`	Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. J. Electron. Test. T. A. García, Antonio J. Acosta, J. M. Mora, J. Ramos, José Luis Huertas
1998	—	`conf`	Efficient self-timed circuits based on weak NMOS-trees. ICECS Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia
1998	Misc	`conf`	Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. VTS T. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos
1995	J	`jnl`	Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
1995	—	`conf`	New CMOS VLSI linear self-timed architectures. ASYNC Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas
1995	J	`jnl`	SODS: a new CMOS differential-type structure. IEEE J. Solid State Circuits Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas
1993	C	`conf`	A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro
1993	—	`conf`	Modeling of real bistables in VHDL. EURO-DAC Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas