Antonio González

365 papers A* 61A 47B 26C 30Misc 9Journal 130Unranked 61

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	ARAS: Adaptive low-cost ReRAM-based accelerator for DNNs. J. Syst. Archit. Mohammad Sabri, Marc Riera, Antonio González
2026	J	`jnl`	Design of a GPU with Heterogeneous Cores for Graphics. CoRR Aurora Tomás, Juan Luis Aragón, Joan-Manuel Parcerisa, Antonio González
2025	J	`jnl`	An energy-efficient near-data processing accelerator for DNNs to optimize memory accesses. J. Syst. Archit. Bahareh Khabbazan, Mohammad Sabri, Marc Riera, Antonio González
2025	J	`jnl`	Analyzing Modern NVIDIA GPU cores. CoRR Rodrigo Huerta, Mojtaba Abaie Shoushtary, José-Lorenzo Cruz, Antonio González
2025	A*	`conf`	Caravan: A Hardware/Software Co-Design for Efficient SIMD Neighbor Search on Point Clouds. ISCA Pedro Henrique Exenberger Becker, Franyell Silfa, José-María Arnau, Antonio González
2025	A*	`conf`	Dissecting and Modeling the Architecture of Modern GPU Cores. MICRO Rodrigo Huerta, Mojtaba Abaie Shoushtary, José-Lorenzo Cruz, Antonio González
2025	B	`conf`	GPU Simulation Acceleration via Parallelization. ISPASS Rodrigo Huerta, Antonio González
2025	J	`jnl`	Hamun: An Approximate Computation Method to Prolong the Lifespan of ReRAM-Based Accelerators. CoRR Mohammad Sabri, Marc Riera, Antonio González
2025	J	`jnl`	Hamun: An approximate computing method to prolong the lifespan of ReRAM-based accelerators. J. Syst. Archit. Mohammad Sabri, Marc Riera, Antonio González
2025	A*	`conf`	IRIS: Unleashing ISP-Software Cooperation to Optimize the Machine Vision Pipeline. HPCA Raúl Taranco, José-María Arnau, Antonio González
2025	J	`jnl`	On the Development of Vehicle Dynamics Active Systems: The Handling Stability Ratio as a Strategic Indicator for Integrating Multiple Actuators. IEEE Access Roberto Aratri, Stefano De Pinto, Giuseppe Guastadisegni, Antonio González, Aldo Sorniotti, Francesco Bottiglione, Giacomo Mantriota
2025	J	`jnl`	Parallelizing a modern GPU simulator. CoRR Rodrigo Huerta, Antonio González
2025	J	`jnl`	Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads. CoRR Bahareh Khabbazan, Marc Riera, Antonio González
2024	J	`jnl`	ARAS: An Adaptive Low-Cost ReRAM-Based Accelerator for DNNs. CoRR Mohammad Sabri, Marc Riera, Antonio González
2024	J	`jnl`	Analyzing and Improving Hardware Modeling of Accel-Sim. CoRR Rodrigo Huerta, Mojtaba Abaie Shoushtary, Antonio González
2024	J	`jnl`	Control Flow Management in Modern GPUs. CoRR Mojtaba Abaie Shoushtary, Jordi Tubella Murgadas, Antonio González
2024	J	`jnl`	Exploiting beam search confidence for energy-efficient speech recognition. J. Supercomput. Dennis Pinto, José-María Arnau, Marc Riera, José-Lorenzo Cruz, Antonio González
2024	A*	`conf`	LIBRA: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering. MICRO Aurora Tomás, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González
2024	A*	`conf`	Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs. ISCA Mojtaba Abaie Shoushtary, José-María Arnau, Jordi Tubella Murgadas, Antonio González
2024	J	`jnl`	Mixture-of-Rookies: Saving DNN computations by predicting ReLU outputs. Microprocess. Microsystems Dennis Pinto, José-María Arnau, Marc Riera, José-Lorenzo Cruz, Antonio González
2024	B	`conf`	ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNNs. ICPP Mohammad Sabri Abrebekoh, Marc Riera Villanueva, Antonio González
2024	J	`jnl`	SIMIL: SIMple Issue Logic for GPUs. Microprocess. Microsystems Rodrigo Huerta, José-Lorenzo Cruz, José-María Arnau, Antonio González
2024	A	`conf`	SLIDEX: A Novel Architecture for Sliding Window Processing. ICS Raúl Taranco, José-María Arnau, Antonio González
2024	J	`jnl`	WaSP: Warp Scheduling to Mimic Prefetching in Graphics Workloads. CoRR Diya Joseph, Juan Luis Aragón, Joan-Manuel Parcerisa, Antonio González
2023	J	`jnl`	A Lightweight, Compiler-Assisted Register File Cache for GPGPU. CoRR Mojtaba Abaie Shoushtary, José-María Arnau, Jordi Tubella Murgadas, Antonio González
2023	J	`jnl`	An Energy-Efficient Near-Data Processing Accelerator for DNNs that Optimizes Data Accesses. CoRR Bahareh Khabbazan, Marc Riera, Antonio González
2023	B	`conf`	Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs. PACT Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González
2023	Misc	`conf`	DNA-TEQ: An Adaptive Exponential Quantization of Tensors for DNN Inference. HiPC Bahareh Khabbazan, Marc Riera, Antonio González
2023	J	`jnl`	DNA-TEQ: An Adaptive Exponential Quantization of Tensors for DNN Inference. CoRR Bahareh Khabbazan, Marc Riera, Antonio González
2023	A	`conf`	Exploiting Kernel Compression on BNNs. DATE Franyell Silfa, José-María Arnau, Antonio González
2023	J	`jnl`	Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads. J. Supercomput. Albert Segura, José-María Arnau, Antonio González
2023	A*	`conf`	K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks. ISCA Pedro Henrique Exenberger Becker, José-María Arnau, Antonio González
2023	J	`jnl`	K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks. CoRR Pedro Henrique Exenberger Becker, José-María Arnau, Antonio González
2023	J	`jnl`	LOCATOR: Low-power ORB accelerator for autonomous cars. J. Parallel Distributed Comput. Raúl Taranco, José-María Arnau, Antonio González
2023	—	`conf`	Lightweight Register File Caching in Collector Units for GPUs. GPGPU@PPoPP Mojtaba Abaie Shoushtary, José-María Arnau, Jordi Tubella Murgadas, Antonio González
2023	B	`conf`	QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures. PACT Bahareh Khabbazan, Marc Riera, Antonio González
2023	J	`jnl`	ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inference. CoRR Mohammad Sabri Abrebekoh, Marc Riera, Antonio González
2023	J	`jnl`	ReuseSense: With Great Reuse Comes Greater Efficiency; Effectively Employing Computation Reuse on General-Purpose CPUs. CoRR Nitesh Narayana GS, Marc Ordoñez, Lokananda Hari, Franyell Silfa, Antonio González
2023	J	`jnl`	SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks. ACM Trans. Embed. Comput. Syst. Reza Yazdani Aminabadi, Olatunji Ruwase, Minjia Zhang, Yuxiong He, José-María Arnau, Antonio González
2023	B	`conf`	SLIDEX: Sliding Window Extension for Image Processing. PACT Raúl Taranco, José-María Arnau, Antonio González
2023	—	`conf`	Simple Out of Order Core for GPGPUs. GPGPU@PPoPP Rodrigo Huerta, José-María Arnau, Antonio González
2023	A*	`conf`	δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant Computations in the Vision Pipeline. MICRO Raúl Taranco, José-María Arnau, Antonio González
2022	J	`jnl`	A Survey of Near-Data Processing Architectures for Neural Networks. Mach. Learn. Knowl. Extr. Mehdi Hassanpour, Marc Riera, Antonio González
2022	J	`jnl`	ASRPU: A Programmable Accelerator for Low-Power Automatic Speech Recognition. CoRR Dennis Pinto, José-María Arnau, Antonio González
2022	J	`jnl`	CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs. J. Syst. Archit. Marc Riera, José-María Arnau, Antonio González
2022	J	`jnl`	DNN pruning with principal component analysis and connection importance estimation. J. Syst. Archit. Marc Riera, José-María Arnau, Antonio González
2022	C	`conf`	DTM-NUCA: Dynamic Texture Mapping-NUCA for Energy-Efficient Graphics Rendering. PDP David Corbalán-Navarro, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González
2022	A*	`conf`	DTexL: Decoupled Raster Pipeline for Texture Locality. MICRO Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González
2022	J	`jnl`	Dynamic Sampling Rate: Harnessing Frame Coherence in Graphics Applications for Energy-Efficient GPUs. CoRR Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Antonio González
2022	J	`jnl`	Dynamic sampling rate: harnessing frame coherence in graphics applications for energy-efficient GPUs. J. Supercomput. Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Antonio González
2022	J	`jnl`	E-BATCH: Energy-Efficient and High-Throughput RNN Batching. ACM Trans. Archit. Code Optim. Franyell Silfa, José-María Arnau, Antonio González
2022	J	`jnl`	Energy-Efficient Stream Compaction Through Filtering and Coalescing Accesses in GPGPU Memory Partitions. IEEE Trans. Computers Albert Segura, José-María Arnau, Antonio González
2022	J	`jnl`	Exploiting Kernel Compression on BNNs. CoRR Franyell Silfa, José-María Arnau, Antonio González
2022	B	`conf`	MEGsim: A Novel Methodology for Efficient Simulation of Graphics Workloads in GPUs. ISPASS Jorge Ortiz, David Corbalán-Navarro, Juan L. Aragón, Antonio González
2022	J	`jnl`	Mixture-of-Rookies: Saving DNN Computations by Predicting ReLU Outputs. CoRR Dennis Pinto, José-María Arnau, Antonio González
2022	J	`jnl`	Omega-Test: A Predictive Early-Z Culling to Improve the Graphics Pipeline Energy-Efficiency. IEEE Trans. Vis. Comput. Graph. David Corbalán-Navarro, Juan L. Aragón, Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Antonio González
2022	J	`jnl`	Saving RNN Computations with a Neuron-Level Fuzzy Memoization Scheme. CoRR Franyell Silfa, José-María Arnau, Antonio González
2022	A*	`conf`	TCOR: A Tile Cache with Optimal Replacement. HPCA Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González
2022	J	`jnl`	Triangle Dropping: An Occluded-geometry Predictor for Energy-efficient Mobile GPUs. ACM Trans. Archit. Code Optim. David Corbalán-Navarro, Juan L. Aragón, Martí Anglada, Joan-Manuel Parcerisa, Antonio González
2022	B	`conf`	XFeatur: Hardware Feature Extraction for DNN Auto-tuning. ISPASS Jorge Sierra Acosta, Andreas Diavastos, Antonio González
2021	C	`conf`	A Low-Power Hardware Accelerator for ORB Feature Extraction in Self-Driving Cars. SBAC-PAD Raúl Taranco, José-María Arnau, Antonio González
2021	J	`jnl`	A Survey of Near-Data Processing Architectures for Neural Networks. CoRR Mehdi Hassanpour, Marc Riera, Antonio González
2021	J	`jnl`	CREW: Computation Reuse and Efficient Weight Storage for Hardware-accelerated MLPs and RNNs. CoRR Marc Riera, José-María Arnau, Antonio González
2021	J	`jnl`	Exploiting Beam Search Confidence for Energy-Efficient Speech Recognition. CoRR Dennis Pinto, José-María Arnau, Antonio González
2021	J	`jnl`	Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design. IEEE Trans. Sustain. Comput. Martí Anglada, Ramon Canal, Juan L. Aragón, Antonio González
2020	Misc	`conf`	Boosting LSTM Performance Through Dynamic Precision Selection. HiPC Franyell Silfa, José-María Arnau, Antonio González
2020	—	`conf`	Demystifying Power and Performance Bottlenecks in Autonomous Driving Systems. IISWC Pedro Henrique Exenberger Becker, José-María Arnau, Antonio González
2020	J	`jnl`	Design and Evaluation of an Ultra Low-power Human-quality Speech Recognition System. ACM Trans. Archit. Code Optim. Dennis Pinto, José-María Arnau, Antonio González
2020	J	`jnl`	E-BATCH: Energy-Efficient and High-Throughput RNN Batching. CoRR Franyell Silfa, José-María Arnau, Antonio González
2020	J	`jnl`	Irregular Accesses Reorder Unit: Improving GPGPU Memory Coalescing for Graph-Based Workloads. CoRR Albert Segura, José-María Arnau, Antonio González
2020	J	`jnl`	LAWS: Locality-AWare Scheme for Automatic Speech Recognition. IEEE Trans. Computers Reza Yazdani, José-María Arnau, Antonio González
2019	J	`jnl`	(Pen-) Ultimate DNN Pruning. CoRR Marc Riera, José-María Arnau, Antonio González
2019	J	`jnl`	A Low-Power, High-Performance Speech Recognition Accelerator. IEEE Trans. Computers Reza Yazdani, José-María Arnau, Antonio González
2019	J	`jnl`	Boosting LSTM Performance Through Dynamic Precision Selection. CoRR Franyell Silfa, José-María Arnau, Antonio González
2019	J	`jnl`	CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference. IEEE Micro Marc Riera, José-María Arnau, Antonio González
2019	A*	`conf`	Early Visibility Resolution for Removing Ineffectual Computations in the Graphics Pipeline. HPCA Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Antonio González
2019	J	`jnl`	LSTM-Sharp: An Adaptable, Energy-Efficient Hardware Accelerator for Long Short-Term Memory. CoRR Reza Yazdani, Olatunji Ruwase, Minjia Zhang, Yuxiong He, José-María Arnau, Antonio González
2019	A*	`conf`	Neuron-Level Fuzzy Memoization in RNNs. MICRO Franyell Silfa, Gem Dot, José-María Arnau, Antonio González
2019	B	`conf`	POSTER: Leveraging Run-Time Feedback for Efficient ASR Acceleration. PACT Reza Yazdani, José-María Arnau, Antonio González
2019	A*	`conf`	Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline. HPCA Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Pedro Marcuello, Antonio González
2019	A*	`conf`	SCU: a GPU stream compaction unit for graph processing. ISCA Albert Segura, José-María Arnau, Antonio González
2019	J	`jnl`	SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems. IEEE Trans. Computers Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Martí Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo
2019	J	`jnl`	Visibility Rendering Order: Improving Energy Efficiency on Mobile GPUs through Frame Coherence. IEEE Trans. Parallel Distributed Syst. Enrique de Lucas, Pedro Marcuello, Joan-Manuel Parcerisa, Antonio González
2018	J	`jnl`	2018 International Symposium on Computer Architecture Influential Paper Award. IEEE Micro Antonio González
2018	A*	`conf`	A Novel Register Renaming Technique for Out-of-Order Processors. HPCA Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González
2018	A*	`conf`	Computation Reuse in DNNs by Exploiting Input Similarity. ISCA Marc Riera, José-María Arnau, Antonio González
2018	B	`conf`	E-PUR: an energy-efficient processing unit for recurrent neural networks. PACT Franyell Silfa, Gem Dot, José-María Arnau, Antonio González
2018	J	`jnl`	Performance Analysis and Optimization of Automatic Speech Recognition. IEEE Trans. Multi Scale Comput. Syst. Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González
2018	J	`jnl`	Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline. CoRR Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Pedro Marcuello, Antonio González
2018	A*	`conf`	The Dark Side of DNN Pruning. ISCA Reza Yazdani, Marc Riera, José-María Arnau, Antonio González
2018	J	`jnl`	Trends in Processor Architecture. CoRR Antonio González
2017	B	`conf`	An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition. PACT Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González
2017	J	`jnl`	E-PUR: An Energy-Efficient Processing Unit for Recurrent Neural Networks. CoRR Franyell Silfa, Gem Dot, José-María Arnau, Antonio González
2017	J	`jnl`	Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator. IEEE Micro Reza Yazdani, Albert Segura, José-María Arnau, Antonio González
2017	A*	`conf`	MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment. ISCA Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio González
2017	A	`conf`	Removing checks in dynamically typed languages through efficient profiling. CGO Gem Dot, Alejandro Martínez, Antonio González
2017	J	`jnl`	Shared resource aware scheduling on power-constrained tiled many-core processors. J. Parallel Distributed Comput. Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout
2017	A*	`conf`	UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST composition. MICRO Reza Yazdani, José-María Arnau, Antonio González
2016	J	`jnl`	A Case for Acoustic Wave Detectors for Soft-Errors. IEEE Trans. Computers Gaurang Upasani, Xavier Vera, Antonio González
2016	A	`conf`	A detailed methodology to compute Soft Error Rates in advanced technologies. DATE Marc Riera, Ramon Canal, Jaume Abella, Antonio González
2016	J	`jnl`	An Energy-Efficient Memory Unit for Clustered Microarchitectures. IEEE Trans. Computers Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González
2016	A*	`conf`	An ultra low-power hardware accelerator for automatic speech recognition. MICRO Reza Yazdani, Albert Segura, José-María Arnau, Antonio González
2016	J	`jnl`	Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment. ACM Trans. Comput. Syst. Rakesh Kumar, Alejandro Martínez, Antonio González
2016	A	`conf`	Cross-layer system reliability assessment framework for hardware faults. ITC Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale
2016	Misc	`conf`	ERICO: Effective Removal of Inline Caching Overhead in Dynamic Typed Languages. HiPC Gem Dot, Alejandro Martínez, Antonio González
2016	C	`conf`	MASkIt: Soft error rate estimation for combinational circuits. ICCD Martí Anglada, Ramon Canal, Juan L. Aragón, Antonio González
2016	—	`conf`	Quantitative characterization of the software layer of a HW/SW co-designed processor. IISWC José Cano, Rakesh Kumar, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, Antonio González
2016	J	`jnl`	Scalability of Broadcast Performance in Wireless Network-on-Chip. IEEE Trans. Parallel Distributed Syst. Sergi Abadal, Albert Mestres, Mario Nemirovsky, Heekwan Lee, Antonio González, Eduard Alarcón, Albert Cabellos-Aparicio
2016	—	`conf`	Shared resource aware scheduling on power-constrained tiled many-core processors. Conf. Computing Frontiers Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout
2015	C	`conf`	Analysis and Optimization of Engines for Dynamically Typed Languages. SBAC-PAD Gem Dot, Alejandro Martínez, Antonio González
2015	—	`conf`	Chrysso: an integrated power manager for constrained many-core processors. Conf. Computing Frontiers Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Trevor E. Carlson, Kenzo Van Craeynest, Jordi Tubella, Antonio González, Lieven Eeckhout
2015	A*	`conf`	Ultra-low power render-based collision detection for CPU/GPU systems. MICRO Enrique de Lucas, Pedro Marcuello, Joan-Manuel Parcerisa, Antonio González
2014	—	`conf`	Accurate off-line phase classification for HW/SW co-designed processors. Conf. Computing Frontiers Aleksandar Brankovic, Kyriakos Stavrou, Enric Gibert, Antonio González
2014	—	`conf`	Author retrospective for the dual data cache. ICS 25th Anniversary Antonio González, Carlos Aliagas
2014	A*	`conf`	Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. ISCA Gaurang Upasani, Xavier Vera, Antonio González
2014	C	`conf`	Cross-layer early reliability evaluation: Challenges and promises. IOLTS Stefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Antonio González, Ramon Canal, Riccardo Mariani, M. Pipponzi, Arnaud Grasset, Philippe Bonnot, Frank Reichenbach, Gulzaib Rafiq, Trond Loekstad
2014	J	`jnl`	Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment. ACM Trans. Archit. Code Optim. Rakesh Kumar, Alejandro Martínez, Antonio González
2014	C	`conf`	Framework for economical error recovery in embedded cores. IOLTS Gaurang Upasani, Xavier Vera, Antonio González
2014	A	`conf`	INFORMER: An integrated framework for early-stage memory robustness analysis. DATE Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio
2014	A	`conf`	Warm-Up Simulation Methodology for HW/SW Co-Designed Processors. CGO Aleksandar Brankovic, Kyriakos Stavrou, Enric Gibert, Antonio González
2014	C	`conf`	iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches. ICCD Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio
2013	A*	`conf`	Deconfigurable microprocessor architectures for silicon debug acceleration. ISCA Nikos Foutris, Dimitris Gizopoulos, Xavier Vera, Antonio González
2013	C	`conf`	Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment. SBAC-PAD Rakesh Kumar, Alejandro Martínez, Antonio González
2013	—	`conf`	Effectiveness of hybrid recovery techniques on parametric failures. ISQED Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio
2013	—	`conf`	Performance analysis and predictability of the software layer in dynamic binary translators/optimizers. Conf. Computing Frontiers Aleksandar Brankovic, Kyriakos Stavrou, Enric Gibert, Antonio González
2013	C	`conf`	Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery. IOLTS Gaurang Upasani, Xavier Vera, Antonio González
2013	J	`jnl`	Replacement techniques for dynamic NUCA cache designs on CMPs. J. Supercomput. Javier Lira, Carlos Molina, Ryan N. Rakvic, Antonio González
2013	Misc	`conf`	Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment. HiPC Rakesh Kumar, Alejandro Martínez, Antonio González
2013	—	`conf`	Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment. HPCC/EUC Rakesh Kumar, Alejandro Martínez, Antonio González
2012	J	`jnl`	A HW/SW Co-designed Programmable Functional Unit. IEEE Comput. Archit. Lett. Abhishek Deb, Josep M. Codina, Antonio González
2012	C	`conf`	A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. ICCD Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio
2012	B	`conf`	DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support. VEE Demos Pavlou, Enric Gibert, Fernando Latorre, Antonio González
2012	B	`conf`	Exploiting temporal locality in network traffic using commodity multi-cores. ISPASS Govind Sreekar Shenoy, Jordi Tubella, Antonio González
2012	—	`conf`	Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks. IPDPS Workshops Govind Sreekar Shenoy, Jordi Tubella, Antonio González
2012	J	`jnl`	Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells. Integr. Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González
2012	B	`conf`	Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic. MASCOTS Govind Sreekar Shenoy, Jordi Tubella, Antonio González
2012	C	`conf`	Improving the Resilience of an IDS against Performance Throttling Attacks. SecureComm Govind Sreekar Shenoy, Jordi Tubella, Antonio González
2012	A*	`conf`	Setting an error detection infrastructure with low cost acoustic wave detectors. ISCA Gaurang Upasani, Xavier Vera, Antonio González
2012	B	`conf`	Speculative dynamic vectorization for HW/SW co-designed processors. PACT Rakesh Kumar, Alejandro Martínez, Antonio González
2012	J	`jnl`	The migration prefetcher: Anticipating data promotion in dynamic NUCA caches. ACM Trans. Archit. Code Optim. Javier Lira, Timothy M. Jones, Carlos Molina, Antonio González
2011	A*	`ed.`	38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA ISCA Ravi R. Iyer, Qing Yang, Antonio González
2011	—	`conf`	A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit. Interaction between Compilers and Computer Architectures Abhishek Deb, Josep M. Codina, Antonio González
2011	A	`conf`	A Performance and Area Efficient Architecture for Intrusion Detection Systems. IPDPS Govind Sreekar Shenoy, Jordi Tubella, Antonio González
2011	C	`conf`	A Power-Efficient Co-designed Out-of-Order Processor. SBAC-PAD Abhishek Deb, Josep M. Codina, Antonio González
2011	A*	`conf`	Accelerating microprocessor silicon validation by exposing ISA diversity. MICRO Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González
2011	B	`conf`	Beforehand Migration on D-NUCA Caches. PACT Javier Lira, Timothy M. Jones, Carlos Molina, Antonio González
2011	J	`jnl`	CROB: Implementing a Large Instruction Window through Compression. Trans. High Perform. Embed. Archit. Compil. Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González
2011	J	`jnl`	Compiler Directed Issue Queue Energy Reduction. Trans. High Perform. Embed. Archit. Compil. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González
2011	—	`conf`	Design of complex circuits using the Via-Configurable transistor array regular layout fabric. SoCC Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González
2011	C	`conf`	Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors. ICCD Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio
2011	A*	`conf`	Fg-STP: Fine-Grain Single Thread Partitioning on Multicores. HPCA Rakesh Ranjan, Fernando Latorre, Pedro Marcuello, Antonio González
2011	B	`conf`	Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations. LCTES Indu Bhagat, Enric Gibert, F. Jesús Sánchez, Antonio González
2011	A	`conf`	HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors. IPDPS Javier Lira, Carlos Molina, Antonio González
2011	A*	`conf`	Hardware/software-based diagnosis of load-store queues using expandable activity logs. HPCA Javier Carretero, Xavier Vera, Jaume Abella, Tanausú Ramírez, Matteo Monchiero, Antonio González
2011	—	`conf`	Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells. ACM Great Lakes Symposium on VLSI Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González
2011	J	`jnl`	Implementing End-to-End Register Data-Flow Continuous Self-Test. IEEE Trans. Computers Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González
2011	Misc	`conf`	Implementing a hybrid SRAM / eDRAM NUCA architecture. HiPC Javier Lira, Carlos Molina, David M. Brooks, Antonio González
2011	—	`conf`	Moore's law implications on energy reduction. HiPEAC Antonio González
2011	C	`conf`	New reliability mechanisms in memory design for sub-22nm technologies. IOLTS Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber
2011	—	`conf`	SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion. Conf. Computing Frontiers Abhishek Deb, Josep M. Codina, Antonio González
2011	—	`conf`	TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies. FET Ramon Canal, Antonio Rubio, A. Asenov, A. Brown, Miguel Miranda, Paul Zuber, Antonio González, Xavier Vera
2011	A	`conf`	Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems. ISLPED Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González
2010	A*	`conf`	A Dynamically Adaptable Hardware Transactional Memory. MICRO Marc Lupon, Grigorios Magklis, Antonio González
2010	A	`conf`	Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. DATE Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio
2010	J	`jnl`	Energy efficiency via thread fusion and value reuse. IET Comput. Digit. Tech. Ryan N. Rakvic, José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Antonio González
2010	A*	`conf`	High-Performance low-vcc in-order core. HPCA Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González
2010	J	`jnl`	Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum. IEEE Trans. Computers Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González
2010	A	`conf`	MODEST: a model for energy estimation under spatio-temporal variability. ISLPED Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio
2010	A	`conf`	MT-SBST: Self-test optimization in multithreaded multicore architectures. ITC Nikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Andreas Apostolakis, Xavier Vera, Antonio González
2010	—	`book`	Processor Microarchitecture: An Implementation Perspective Processor Microarchitecture Antonio González, Fernando Latorre, Grigorios Magklis
2010	A	`conf`	The auction: optimizing banks usage in Non-Uniform Cache Architectures. ICS Javier Lira, Carlos Molina, Antonio González
2010	J	`jnl`	Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors. ACM Trans. Archit. Code Optim. Ryan N. Rakvic, Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González
2010	C	`conf`	VCTA: A Via-Configurable Transistor Array regular fabric. VLSI-SoC Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González
2009	J	`jnl`	AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures. IEEE Trans. Computers Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli
2009	B	`conf`	Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. PACT Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González
2009	A*	`conf`	Boosting single-thread performance in multi-core systems through fine-grain multi-threading. ISCA Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González
2009	A*	`conf`	End-to-end register data-flow continuous self-test. ISCA Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González
2009	J	`jnl`	Energy-efficient register caching with compiler assistance. ACM Trans. Archit. Code Optim. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin
2009	J	`jnl`	Exploring the limits of early register release: Exploiting compiler analysis. ACM Trans. Archit. Code Optim. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin
2009	B	`conf`	FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery. PACT Marc Lupon, Grigorios Magklis, Antonio González
2009	—	`conf`	Key Microarchitectural Innovations for Future Microprocessors. ARCS Antonio González
2009	C	`conf`	LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors. ICCD Javier Lira, Carlos Molina, Antonio González
2009	—	`conf`	Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs. Euro-Par Javier Lira, Carlos Molina, Antonio González
2009	A*	`conf`	Low Vccmin fault-tolerant cache with highly predictable performance. MICRO Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González
2009	C	`conf`	Online error detection and correction of erratic bits in register files. IOLTS Xavier Vera, Jaume Abella, Javier Carretero, Pedro Chaparro, Antonio González
2009	Misc	`conf`	P-slice based efficient speculative multithreading. HiPC Rakesh Ranjan, Pedro Marcuello, Fernando Latorre, Antonio González
2009	J	`jnl`	Reducing Soft Errors through Operand Width Aware Policies. IEEE Trans. Dependable Secur. Comput. Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González
2009	J	`jnl`	Selective replication: A lightweight technique for soft errors. ACM Trans. Comput. Syst. Xavier Vera, Jaume Abella, Javier Carretero, Antonio González
2009	B	`conf`	Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs. ICPP Matteo Monchiero, Ramon Canal, Antonio González
2008	A	`conf`	A software-hardware hybrid steering mechanism for clustered microarchitectures. IPDPS Qiong Cai, Josep M. Codina, José González, Antonio González
2008	A	`conf`	Efficient resources assignment schemes for clustered multithreaded processors. IPDPS Fernando Latorre, José González, Antonio González
2008	B	`conf`	Meeting points: using thread criticality to adapt multicore hardware to parallel regions. PACT Qiong Cai, José González, Ryan N. Rakvic, Grigorios Magklis, Pedro Chaparro, Antonio González
2008	J	`jnl`	Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distributed Syst. Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen
2008	C	`conf`	On-Line Failure Detection and Confinement in Caches. IOLTS Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González
2008	J	`jnl`	Power/Performance/Thermal Design-Space Exploration for Multicore Architectures. IEEE Trans. Parallel Distributed Syst. Matteo Monchiero, Ramon Canal, Antonio González
2008	J	`jnl`	Refueling: Preventing Wire Degradation due to Electromigration. IEEE Micro Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz
2008	A	`conf`	Thread fusion. ISLPED José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Ryan N. Rakvic, Antonio González
2008	—	`conf`	Version management alternatives for hardware transactional memory. MEDEA@PACT Marc Lupon, Grigorios Magklis, Antonio González
2007	—	`conf`	Building a large instruction window through ROB compression. MEDEA@PACT Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González
2007	B	`conf`	Early Register Release for Out-of-Order Processors with RegisterWindows. PACT Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González
2007	C	`conf`	Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. IOLTS Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González
2007	J	`jnl`	Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. IEEE Micro Ronny Ronen, Antonio González
2007	A	`conf`	Heterogeneous Clustered VLIW Microarchitectures. CGO Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
2007	A*	`conf`	Improving Branch Prediction and Predicated Execution in Out-of-Order Processors. HPCA Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González
2007	A*	`conf`	Penelope: The NBTI-Aware Processor. MICRO Jaume Abella, Xavier Vera, Antonio González
2007	J	`jnl`	Reliability: Fallacy or Reality? IEEE Micro Antonio González, Scott A. Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, Joshua J. Yi
2007	J	`jnl`	Understanding the Thermal Implications of Multi-Core Architectures. IEEE Trans. Parallel Distributed Syst. Pedro Chaparro, José González, Grigorios Magklis, Qiong Cai, Antonio González
2007	A	`conf`	Virtual Cluster Scheduling Through the Scheduling Graph. CGO Josep M. Codina, F. Jesús Sánchez, Antonio González
2006	J	`jnl`	A dynamically reconfigurable cache for multithreaded processors. J. Embed. Comput. Alex Settle, Dan Connors, Enric Gibert, Antonio González
2006	J	`jnl`	Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. IEEE Trans. Computers Juan L. Aragón, José M. González, Antonio González
2006	A	`conf`	Design space exploration for multicore architectures: a power/performance/thermal view. ICS Matteo Monchiero, Ramon Canal, Antonio González
2006	A	`conf`	Empowering a helper cluster through data-width aware instruction selection policies. IPDPS Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio González
2006	J	`jnl`	Exploiting Narrow Values for Soft Error Tolerance. IEEE Comput. Archit. Lett. Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González
2006	A	`conf`	Heterogeneous way-size cache. ICS Jaume Abella, Antonio González
2006	J	`jnl`	Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
2006	A	`conf`	Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. ISLPED Grigorios Magklis, Pedro Chaparro, José González, Antonio González
2006	J	`jnl`	Instruction scheduling for a clustered VLIW processor with a word-interleaved cache. Concurr. Comput. Pract. Exp. Enric Gibert, F. Jesús Sánchez, Antonio González
2006	A	`conf`	SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. IPDPS Jaume Abella, Antonio González
2006	A	`conf`	Selective predicate prediction for out-of-order processors. ICS Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González
2005	J	`jnl`	An accurate cost model for guiding data locality transformations. ACM Trans. Program. Lang. Syst. Xavier Vera, Jaume Abella, Josep Llosa, Antonio González
2005	—	`conf`	Compiler Directed Early Register Release. IEEE PACT Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin
2005	—	`conf`	Compiler analysis for trace-level speculative multithreaded architectures. Interaction between Compilers and Computer Architectures Carlos Molina, Antonio González, Jordi Tubella
2005	A	`conf`	Control-Flow Independence Reuse via Dynamic Vectorization. IPDPS Alex Pajuelo, Antonio González, Mateo Valero
2005	A*	`conf`	Demystifying on-the-fly spill code. PLDI Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
2005	J	`jnl`	Distributed Data Cache Designs for Clustered VLIW Processors. IEEE Trans. Computers Enric Gibert, F. Jesús Sánchez, Antonio González
2005	A*	`conf`	Distributing the Frontend for Temperature Reduction. HPCA Pedro Chaparro, Grigorios Magklis, José González, Antonio González
2005	J	`jnl`	Hardware support for early register release. Int. J. High Perform. Comput. Netw. Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
2005	J	`jnl`	IATAC: a smart predictor to turn-off L2 cache lines. ACM Trans. Archit. Code Optim. Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle
2005	A	`conf`	Inherently Workload-Balanced Clustered Microarchitecture. IPDPS Jaume Abella, Antonio González
2005	C	`conf`	Memory Bank Predictors. ICCD Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González
2005	A*	`conf`	Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. PLDI Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen
2005	J	`jnl`	On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. IEEE Trans. Parallel Distributed Syst. Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato
2005	—	`conf`	Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures. ISHPC Carlos Molina, Jordi Tubella, Antonio González
2005	A*	`conf`	Software Directed Issue Queue Power Reduction. HPCA Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González
2005	J	`jnl`	Speculative execution for hiding memory latency. SIGARCH Comput. Archit. News Alex Pajuelo, Antonio González, Mateo Valero
2005	—	`conf`	The Mitosis Speculative Multithreaded Architectures. PARCO Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González
2005	—	`conf`	Value Compression for Efficient Computation. Euro-Par Ramon Canal, Antonio González, James E. Smith
2005	—	`conf`	Variable-Based Multi-module Data Caches for Clustered VLIW Processors. IEEE PACT Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González
2004	J	`jnl`	A fast and accurate framework to analyze and optimize cache memory behavior. ACM Trans. Program. Lang. Syst. Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González
2004	A	`conf`	Back-end assignment schemes for clustered multithreaded processors. ICS Fernando Latorre, José González, Antonio González
2004	—	`conf`	Cache organizations for clustered microarchitectures. WMPI José González, Fernando Latorre, Antonio González
2004	C	`conf`	Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. ICCD Grigorios Magklis, José González, Antonio González
2004	J	`jnl`	Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
2004	A*	`conf`	Low-Complexity Distributed Issue Queue. HPCA Jaume Abella, Antonio González
2004	J	`jnl`	Removing communications in clustered microarchitectures through instruction replication. ACM Trans. Archit. Code Optim. Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
2004	A	`conf`	Software-Controlled Operand-Gating. CGO Ramon Canal, Antonio González, James E. Smith
2004	—	`conf`	Speculative execution for hiding memory latency. MEDEA@PACT Alex Pajuelo, Antonio González, Mateo Valero
2004	C	`conf`	Thermal-Aware Clustered Microarchitectures. ICCD Pedro Chaparro, José González, Antonio González
2004	J	`jnl`	Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism. IEEE Trans. Computers Pedro Marcuello, Antonio González, Jordi Tubella
2003	A*	`conf`	A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
2003	C	`conf`	Dynamic Cluster Resizing. ICCD José González, Antonio González
2003	A*	`conf`	Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. MICRO Enric Gibert, F. Jesús Sánchez, Antonio González
2003	A*	`conf`	Instruction Replication for Clustered Microarchitectures. MICRO Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
2003	A	`conf`	Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. CGO Enric Gibert, F. Jesús Sánchez, Antonio González
2003	A	`conf`	Non redundant data cache. ISLPED Carlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella
2003	C	`conf`	On Reducing Register Pressure and Energy in Multiple-Banked Register Files. ICCD Jaume Abella, Antonio González
2003	—	`conf`	Optimizing Program Locality Through CMEs and GAs. IEEE PACT Xavier Vera, Jaume Abella, Antonio González, Josep Llosa
2003	C	`conf`	Power Efficient Data Cache Designs. ICCD Jaume Abella, Antonio González
2003	J	`jnl`	Power- and Complexity-Aware Issue Queue Designs. IEEE Micro Jaume Abella, Ramon Canal, Antonio González
2003	Misc	`conf`	Power-Aware Adaptive Issue Queue and Register File. HiPC Jaume Abella, Antonio González
2003	A*	`conf`	Power-Aware Control Speculation through Selective Throttling. HPCA Juan L. Aragón, José González, Antonio González
2003	A	`ed.`	Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003 ICS Utpal Banerjee, Kyle A. Gallivan, Antonio González
2003	—	`conf`	Value Compression to Reduce Power in Data Caches. Euro-Par Carles Aliagas, Carlos Molina, Montse Garcia, Antonio González, Jordi Tubella
2002	A	`conf`	A comparative study of modulo scheduling techniques. ICS Josep M. Codina, Josep Llosa, Antonio González
2002	A	`conf`	An interleaved cache clustered VLIW processor. ICS Enric Gibert, F. Jesús Sánchez, Antonio González
2002	A	`conf`	Dual path instruction processing. ICS Juan L. Aragón, José González, Antonio González, James E. Smith
2002	A*	`conf`	Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor. MICRO Enric Gibert, F. Jesús Sánchez, Antonio González
2002	—	`conf`	Efficient Interconnects for Clustered Microarchitectures. IEEE PACT Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato
2002	J	`jnl`	Errata on "Measuring Experimental Error in Microprocessor Simulation". SIGARCH Comput. Archit. News Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González, Mateo Valero
2002	—	`conf`	Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. IEEE PACT Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli
2002	B	`conf`	Hardware Schemes for Early Register Release. ICPP Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
2002	J	`jnl`	Hypercube Algorithms on Mesh Connected Multicomputers. IEEE Trans. Parallel Distributed Syst. Luis Díaz de Cerio, Miguel Valero-García, Antonio González
2002	—	`conf`	Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. ICPP Workshops Jaume Abella, Antonio González, Josep Llosa, Xavier Vera
2002	—	`conf`	Near-Optimal Padding for Removing Conflict Misses. LCPC Xavier Vera, Josep Llosa, Antonio González
2002	A*	`conf`	Speculative Dynamic Vectorization. ISCA Alex Pajuelo, Antonio González, Mateo Valero
2002	A*	`conf`	Thread-Spawning Schemes for Speculative Multithreading. HPCA Pedro Marcuello, Antonio González
2002	C	`conf`	Trace-Level Speculative Multithreaded Architecture. ICCD Carlos Molina, Antonio González, Jordi Tubella
2001	—	`conf`	A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. IEEE PACT Josep M. Codina, F. Jesús Sánchez, Antonio González
2001	J	`jnl`	CALMANT: A Systematic Method for the Execution of Hypercube Algorithms in Multiprocessor Systems. Computación y Sistemas Luis Díaz de Cerio, Miguel Valero-García, Antonio González, Dolors Royo
2001	J	`jnl`	CALMANT: Un Método Sistemático para la Ejecución de Algoritmos Hipercubo en Sistemas Multiprocesador. Computación y Sistemas Luis Díaz de Cerio, Miguel Valero-García, Antonio González, Dolors Royo
2001	J	`jnl`	Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache . J. Instr. Level Parallelism F. Jesús Sánchez, Antonio González
2001	Misc	`conf`	Confidence Estimation for Branch Prediction Reversal. HiPC Juan L. Aragón, José González, José M. García, Antonio González
2001	J	`jnl`	Control-Flow Speculation through Value Prediction. IEEE Trans. Computers José González, Antonio González
2001	J	`jnl`	Dynamic Code Partitioning for Clustered Architectures. Int. J. Parallel Program. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
2001	A*	`conf`	Energy-effective issue logic. ISCA Daniele Folegnani, Antonio González
2001	A*	`conf`	Graph-partitioning based instruction scheduling for clustered processors. MICRO Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González
2001	J	`jnl`	Implementing the one-sided Jacobi method on a 2D/3D mesh multicomputer. Parallel Comput. Dolors Royo, Miguel Valero-García, Antonio González
2001	J	`jnl`	Improving Latency Tolerance of Multithreading through Decoupling. IEEE Trans. Computers Joan-Manuel Parcerisa, Antonio González
2001	J	`jnl`	Lifetime-Sensitive Modulo Scheduling in a Production Environment. IEEE Trans. Computers Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt
2001	A	`conf`	Reducing the complexity of the issue logic. ICS Ramon Canal, Antonio González
2001	C	`conf`	Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. ICCD Juan L. Aragón, José González, José M. García, Antonio González
2000	—	`conf`	A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). Euro-Par Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo
2000	A	`conf`	A Quantitative Assessment of Thread-Level Speculation Techniques. IPDPS Pedro Marcuello, Antonio González
2000	A	`conf`	A low-complexity issue logic. ICS Ramon Canal, Antonio González
2000	B	`conf`	An efficient solver for Cache Miss Equations. ISPASS Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa
2000	J	`jnl`	Analyzing Data Locality in Numeric Applications. IEEE Micro F. Jesús Sánchez, Antonio González
2000	—	`conf`	Complete Exchange Algorithms for Meshes and Tori Using a Systematic Approach (Research Note). Euro-Par Luis Díaz de Cerio, Miguel Valero-García, Antonio González
2000	A*	`conf`	Dynamic Cluster Assignment Mechanisms. HPCA Ramon Canal, Joan-Manuel Parcerisa, Antonio González
2000	J	`jnl`	Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
2000	—	`conf`	Instruction Scheduling for Clustered VLIW Architectures. ISSS F. Jesús Sánchez, Antonio González
2000	A*	`conf`	Modulo scheduling for a fully-distributed clustered VLIW architecture. MICRO F. Jesús Sánchez, Antonio González
2000	A*	`conf`	Multiple-banked register file architectures. ISCA José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham
2000	J	`jnl`	Optimizing cache miss equations polyhedra. SIGARCH Comput. Archit. News Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa
2000	A*	`conf`	Reducing wire delay penalty through value prediction. MICRO Joan-Manuel Parcerisa, Antonio González
2000	B	`conf`	The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. ICPP F. Jesús Sánchez, Antonio González
2000	A*	`conf`	Very low power pipelines using significance compression. MICRO Ramon Canal, Antonio González, James E. Smith
1999	—	`conf`	A Cost-Effective Clustered Architecture. IEEE PACT Ramon Canal, Joan-Manuel Parcerisa, Antonio González
1999	A	`conf`	A locality sensitive multi-module cache with explicit management. International Conference on Supercomputing F. Jesús Sánchez, Antonio González
1999	A	`conf`	Clustered speculative multithreaded processors. International Conference on Supercomputing Pedro Marcuello, Antonio González
1999	—	`conf`	Control-Flow Speculation through Value Prediction for Superscalar Processors. IEEE PACT José González, Antonio González
1999	A*	`conf`	Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
1999	A	`conf`	Dynamic removal of redundant computations. International Conference on Supercomputing Carlos Molina, Antonio González, Jordi Tubella
1999	—	`conf`	Exploiting Speculative Thread-Level Parallelism on a SMT Processor. HPCN Europe Pedro Marcuello, Antonio González
1999	J	`jnl`	Low Communication Overhead Jacobi Algorithms for Eigenvalues Computation on Hypercubes. J. Supercomput. Dolors Royo, Antonio González, Miguel Valero-García
1999	J	`jnl`	Randomized Cache Placement for Eliminating Conflicts. IEEE Trans. Computers Nigel P. Topham, Antonio González
1999	—	`conf`	Reducing Memory Traffic Via Redundant Store Instructions. HPCN Europe Carlos Molina, Antonio González, Jordi Tubella
1999	J	`jnl`	Software Data Prefetching for Software Pipelined Loops. J. Parallel Distributed Comput. F. Jesús Sánchez, Antonio González
1999	A*	`conf`	The Synergy of Multithreading and Access/Execute Decoupling. HPCA Joan-Manuel Parcerisa, Antonio González
1999	B	`conf`	Trace-Level Reuse. ICPP Antonio González, Jordi Tubella, Carlos Molina
1999	A*	`conf`	Value Prediction for Speculative Multithreaded Architectures. MICRO Pedro Marcuello, Jordi Tubella, Antonio González
1998	C	`conf`	A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh. PDP Dolors Royo, Miguel Valero-García, Antonio González
1998	J	`jnl`	A Method for Exploiting Communication/Computation Overlap in Hypercubes. Parallel Comput. Luis Díaz de Cerio, Miguel Valero-García, Antonio González
1998	A*	`conf`	Control Speculation in Multithreaded Processors through Dynamic Loop Detection. HPCA Jordi Tubella, Antonio González
1998	—	`conf`	Data Speculative Multithreaded Architecture. EUROMICRO Pedro Marcuello, Antonio González
1998	J	`jnl`	Data value speculation in superscalar processors. Microprocess. Microsystems José González, Antonio González
1998	—	`conf`	Divide-and-Conquer Algorithms on Two-Dimensional Meshes. Euro-Par Miguel Valero-García, Antonio González, Luis Díaz de Cerio, Dolors Royo
1998	—	`conf`	Fast, Accurate and Flexible Data Locality Analysis. IEEE PACT F. Jesús Sánchez, Antonio González
1998	—	`conf`	Jacobi Orderings for Multi-Port Hypercubes. IPPS/SPDP Dolors Royo, Antonio González, Miguel Valero-García
1998	—	`conf`	Limits of Instruction Level Parallelism with Data Value Speculation. VECPAR José González, Antonio González
1998	J	`jnl`	Modulo Scheduling with Reduced Register Pressure. IEEE Trans. Computers Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
1998	—	`conf`	Software Prefetching for Software Pipelined Loops. HICSS (7) F. Jesús Sánchez, Antonio González
1998	A	`conf`	Speculative Multithreaded Processors. International Conference on Supercomputing Pedro Marcuello, Antonio González, Jordi Tubella
1998	—	`conf`	The Latency Hiding Effectiveness of Decoupled Access/Execute Processors. EUROMICRO Joan-Manuel Parcerisa, Antonio González
1998	A	`conf`	The Potential of Data Value Speculation to Boost ILP. International Conference on Supercomputing José González, Antonio González
1998	A*	`conf`	Virtual-Physical Registers. HPCA Antonio González, José González, Mateo Valero
1997	—	`conf`	A Methodology for User-Oriented Scalability Analysis. ASAP Dolors Royo, Miguel Valero-García, Antonio González, Carme Mari
1997	A*	`conf`	Cache Sensitive Modulo Scheduling. MICRO F. Jesús Sánchez, Antonio González
1997	A	`conf`	Eliminating Cache Conflict Misses through XOR-Based Placement Functions. International Conference on Supercomputing Antonio González, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa
1997	—	`conf`	Memory Address Prediction for Data Speculation. Euro-Par José González, Antonio González
1997	—	`conf`	PARSAR: Parallelisation of a Chirp Scaling Algorithm SAR Processor. Euro-Par Antonio Martínez, Fracisco Fraile, Jordi J. Mallorquí, Leonardo Nogueira, Jordi Gabaldá, Antoni Broquetas, Antonio González
1997	A	`conf`	Speculative Execution via Address Prediction and Data Prefetching. International Conference on Supercomputing José González, Antonio González
1997	—	`conf`	Static Locality Analysis for Cache Management. IEEE PACT F. Jesús Sánchez, Antonio González, Mateo Valero
1997	A*	`conf`	The Design and Performance of a Conflict-Avoiding Cache. MICRO Nigel P. Topham, Antonio González, José González
1997	Misc	`conf`	Virtual registers. HiPC Antonio González, Mateo Valero, José González, Teresa Monreal Arnal
1996	J	`jnl`	Communication Pipelining in Hypercubes. Parallel Process. Lett. Luis Díaz de Cerio, Antonio González, Miguel Valero-García
1996	—	`conf`	Overlapping Communication and Computation in Hypercubes. Euro-Par, Vol. I Luis Díaz de Cerio, Miguel Valero-García, Antonio González
1996	—	`conf`	Swing module scheduling: a lifetime-sensitive approach. IEEE PACT Josep Llosa, Antonio González, Eduard Ayguadé, Mateo Valero
1996	J	`jnl`	The Multipath Architecture for Prolog Programs. Comput. J. Jordi Tubella, Antonio González, E. Elias
1995	A	`conf`	A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. International Conference on Supercomputing Antonio González, Carlos Aliagas, Mateo Valero
1995	J	`jnl`	Executing Algorithms with Hypercube Topology on Torus Multicomputers. IEEE Trans. Parallel Distributed Syst. Antonio González, Miguel Valero-García, Luis Díaz de Cerio
1995	C	`conf`	Exploiting path parallelism in logic programming. PDP Jordi Tubella, Antonio González
1995	A*	`conf`	Hypernode reduction modulo scheduling. MICRO Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
1995	—	`conf`	Load Balancing in a Network Flow Optimization Code. PARA Enric Fontdecaba, Antonio González, Jesús Labarta
1994	B	`conf`	A Partial Breadth-First Execution Model for Prolog. ICTAI Jordi Tubella, Antonio González
1994	—	`conf`	Combining depth-first and breadth-first search in Prolog execution. GULP-PRODE (2) Jordi Tubella, Antonio González
1994	J	`jnl`	Design and Evaluation of an Instruction Cache for Reducing the Cost of Branches. Perform. Evaluation Antonio González
1994	C	`conf`	Parallel Numerical Algorithms. PDP Antonio González
1994	—	`conf`	The Multipath Parallel Execution Model for Prolog. PASCO Antonio González, Jordi Tubella
1993	J	`jnl`	A survey of branch techniques in pipelined processors. Microprocess. Microprogramming Antonio González
1993	J	`jnl`	Chairmen's introduction. Microprocess. Microprogramming Mateo Valero, Jordi Cortadella, Antonio González
1993	J	`jnl`	MEM: A new execution model for Prolog. Microprocess. Microprogramming Jordi Tubella, Antonio González
1993	J	`jnl`	Reducing Branch Delay to Zero in Pipelined Processors. IEEE Trans. Computers Antonio González, José M. Llabería
1993	—	`conf`	The Xor embedding: An embedding of hypercubes onto rings and toruses. ASAP Antonio González, Miguel Valero-García
1989	A	`conf`	Instruction fetch unit for parallel execution of branch instructions. ICS Antonio González, José M. Llabería
1988	J	`jnl`	A mechanism for reducing the cost of branches in RISC architectures. Microprocess. Microprogramming Antonio González, José María Llabería, Jordi Cortadella