Antonio García

51 papers B 11C 1Misc 2Journal 24Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Accelerating configuration of Reconfigurable Intelligent Surfaces through a hardware-enhanced deep learning approach. Comput. Electr. Eng. Rubén Padial-Allué, Alberto Martín-Martín, Antonio García, Encarnación Castillo, José David Fernández-Rodríguez, Marcos Baena-Molina, Luís Parrilla Roure
2025	—	`conf`	1-D Convolutional Autoencoder for Fetal and Maternal ECG Classification Oriented to Hardware Implementation Acceleration. DCIS Rubén Padial-Allué, Alberto Martín-Martín, Encarnación Castillo, Uwe Meyer-Baese, Víctor Toral, Luis Parrilla, Antonio García
2024	J	`jnl`	Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces. Sensors Alberto Martín-Martín, Rubén Padial-Allué, Encarnación Castillo, Luis Parrilla, Ignacio Parellada-Serrano, Alejandro Morán, Antonio García
2024	—	`conf`	Towards efficient hardware digital twins of lithium-ion batteries. DCIS Luís Parrilla Roure, Pablo Rodríguez-Iturriaga, Juan Antonio López-Villanueva, Salvador Rodríguez-Bolívar, Encarnación Castillo, Antonio García
2023	J	`jnl`	Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications. Cryptogr. Luis Parrilla, Antonio García, Encarnación Castillo, Juan Antonio López Ramos, Uwe Meyer-Baese
2022	J	`jnl`	Table-Free Seed Generation for Hardware Newton-Raphson Square Root and Inverse Square Root Implementations in IoT Devices. IEEE Internet Things J. Luis Parrilla, Antonio Lloris, Encarnación Castillo, Antonio García
2021	—	`conf`	Window Polarization in PCA-based Analysis of Non-Invasive Fetal ECG recordings. DCIS Luis Oyarzún, Encarnación Castillo, Luis Parrilla, Antonio García
2020	J	`jnl`	Cost-Effective Printed Electrodes Based on Emerging Materials Applied to Biosignal Acquisition. IEEE Access Víctor Toral, Encarnación Castillo, Andreas Albretch, Francisco J. Romero, Antonio García, Noel Rodriguez, Paolo Lugli, Diego Pedro Morales, Almudena Rivadeneyra
2020	—	`conf`	Privacy-enabled system based on Elliptic Curve Cryptography to reduce risks of contagion in pandemics. DCIS Luis Parrilla, Encarnación Castillo, Antonio García
2019	—	`conf`	Efficient Elliptic Curve Cryptoprocessor for enabling TLS protocol in low-cost reconfigurable SoCs. DCIS Luís Parrilla Roure, Ahmed Mohamed Bellemou, Antonio García, Encarnación Castillo
2019	J	`jnl`	Elliptic Curve Cryptography hardware accelerator for high-performance secure servers. J. Supercomput. Luís Parrilla Roure, José Antonio Álvarez-Bermejo, Encarnación Castillo, Juan Antonio López-Ramos, Diego Pedro Morales, Antonio García
2019	J	`jnl`	Wearable System for Biosignal Acquisition and Monitoring Based on Reconfigurable Technologies. Sensors Víctor Toral, Antonio García, Francisco J. Romero, Diego Pedro Morales, Encarnación Castillo, Luís Parrilla Roure, Francisco M. Gómez-Campos, Antonio Morillas, Alejandro Sánchez
2018	J	`jnl`	Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks. Sensors Luís Parrilla Roure, Encarnación Castillo, Juan Antonio López Ramos, José Antonio Álvarez-Bermejo, Antonio García, Diego Pedro Morales
2017	J	`jnl`	A new area-efficient BCD-digit multiplier. Digit. Signal Process. Encarnación Castillo, Antonio Lloris-Ruíz, Diego Pedro Morales, Luis Parrilla, Antonio García, Guillermo Botella
2017	—	`conf`	Classification Algorithms for Fetal QRS Extraction in Abdominal ECG Signals. IWBBIO (1) Pedro Álvarez, Francisco J. Romero, Antonio García, Luis Parrilla, Encarnación Castillo, Diego Pedro Morales
2016	J	`jnl`	Comments on "Fast architecture for decimal digit multiplication". Microprocess. Microsystems Encarnación Castillo, Antonio Lloris-Ruíz, Antonio García, Luis Parrilla, Diego Pedro Morales
2015	J	`jnl`	Improvements for the applicability of power-watermarking to embedded IP cores protection: e-coreIPP. Digit. Signal Process. Luis Parrilla, Encarnación Castillo, Elias Todorovich, Antonio García, Diego Pedro Morales, Guillermo Botella
2013	J	`jnl`	Efficient wavelet-based ECG processing for single-lead FHR extraction. Digit. Signal Process. Encarnación Castillo, Diego Pedro Morales, Guillermo Botella Juan, Antonio García, Luis Parrilla, Alberto J. Palma
2013	J	`jnl`	Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques. J. Appl. Math. Encarnación Castillo, Diego Pedro Morales, Antonio García, Fernando Martínez-Martí, Luis Parrilla, Alberto J. Palma
2013	—	`conf`	One-step wavelet-based processing for wandering and noise removing in ECG signals. IWBBIO Encarnación Castillo, Diego Pedro Morales, Antonio García, Luis Parrilla, Nuria López-Ruiz, Alberto J. Palma
2012	J	`jnl`	A reconstruction method for electrical capacitance tomography based on image fusion techniques. Digit. Signal Process. Antonio Martínez-Olmos, Guillermo Botella Juan, Encarnación Castillo, Diego Pedro Morales, Jesus Banqueri, Antonio García
2012	J	`jnl`	Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology. Microprocess. Microsystems Uwe Meyer-Bäse, Guillermo Botella Juan, Soumak Mookherjee, Encarnación Castillo, Antonio García
2012	J	`jnl`	Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture. Digit. Signal Process. Guillermo Botella Juan, Uwe Meyer-Bäse, Antonio García, Manuel Rodríguez
2008	B	`conf`	Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. FPL Diego Pedro Morales, Antonio García, Alberto J. Palma, Miguel Ángel Carvajal, Encarnación Castillo, Luis F. Capitán-Vallvey
2008	J	`jnl`	Neuromorphic Configurable Architecture for Robust Motion Estimation. Int. J. Reconfigurable Comput. Guillermo Botella Juan, Manuel Rodríguez, Antonio García, Eduardo Ros
2007	B	`conf`	Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. FPL Diego Pedro Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos, Encarnación Castillo
2007	J	`jnl`	IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. IEEE Trans. Very Large Scale Integr. Syst. Encarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz
2007	B	`conf`	Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. FPL Encarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz
2006	B	`conf`	IPP Watermarking Technique for IP Core Protection on FPL Devices. FPL Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse
2005	—	`conf`	Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. PATMOS Daniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz
2005	B	`conf`	Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. FPL Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz
2005	J	`jnl`	Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology. J. Circuits Syst. Comput. Javier Ramírez, Uwe Meyer-Bäse, Antonio García
2004	B	`conf`	Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. FPL Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García
2004	B	`conf`	Intellectual Property Protection for RNS Circuits on FPGAs. FPL Luis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz
2003	J	`jnl`	A Fast QRNS-Based Algorithm for the DCT and Its Field-Programmable Logic Implementation. J. Circuits Syst. Comput. Javier Ramírez, Antonio García
2003	J	`jnl`	Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies. J. VLSI Signal Process. Javier Ramírez, Uwe Meyer-Bäse, Fred J. Taylor, Antonio García, Antonio Lloris-Ruíz
2003	B	`conf`	Design and Implementation of RNS-Based Adaptive Filters. FPL Javier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz
2003	J	`jnl`	Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic. J. VLSI Signal Process. Javier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz
2002	—	`conf`	A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. PATMOS Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz
2002	B	`conf`	Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. FPL Uwe Meyer-Bäse, Javier Ramírez, Antonio García
2002	B	`conf`	U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation. FPL Javier Ramírez, Antonio García
2001	Misc	`conf`	Design of RNS-based distributed arithmetic DWT filterbanks. ICASSP Javier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Pedro G. Fernández, Antonio Lloris-Ruíz
2001	J	`jnl`	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. J. VLSI Signal Process. Uwe Meyer-Bäse, Antonio García, Fred J. Taylor
2001	—	`conf`	Implementation of the one dimensional discrete cosine transform using the residue number system. ICECS Pedro G. Fernández, Javier Ramírez, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz
2000	C	`conf`	A new architecture to compute the discrete cosine transform using the quadratic residue number system. ISCAS Javier Ramírez Perez de Inestrosa, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz
2000	—	`conf`	An efficient RNS architecture for the computation of discrete wavelet transforms on programmable devices. EUSIPCO Javier Ramírez, Antonio García, Pedro G. Fernández, Antonio Lloris-Ruíz
2000	B	`conf`	Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. FPL Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz
1999	J	`jnl`	A Look-Up Scheme for Scaling in the RNS. IEEE Trans. Computers Antonio García, Antonio Lloris-Ruíz
1999	—	`conf`	RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. ISCAS (1) Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, Fred J. Taylor
1998	Misc	`conf`	Pipelined Hogenauer CIC filters using field-programmable logic and residue number system. ICASSP Antonio García, Uwe Meyer-Baese, Fred J. Taylor
1998	—	`conf`	Pipelined RNS multipliers: an application to scaling. ICECS Antonio García, Antonio Lloris-Ruíz