Antoni Roca

22 papers A* 1A 2B 4C 2Misc 1Journal 9Unranked 3
YearRankTypeTitle / Venue / Authors
2017 A* conf
DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis.
DAC
Sergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella
2016 A conf
Improving performance guarantees in wormhole mesh NoC designs.
DATE
Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla
2016 — conf
Ring Oscillator Clocks and Margins.
ASYNC
Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar
2015 J jnl
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems.
Comput. Electr. Eng.
Antoni Roca, Carles Hernández, Mario Lodde, José Flich
2015 C conf
Reactive clocks with variability-tracking jitter.
ICCD
Jordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar
2014 A conf
A hierarchical approach for generating regular floorplans.
ICCAD
Javier de San Pedro, Jordi Cortadella, Antoni Roca
2014 J jnl
Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead.
IEEE Trans. Computers
José Cano, José Flich, Antoni Roca, José Duato, Marcello Coppola, Riccardo Locatelli
2013 J jnl
Built-in fast gather control network for efficient support of coherence protocols.
IET Comput. Digit. Tech.
Mario Lodde, Antoni Roca, José Flich
2013 J jnl
Silicon-aware distributed switch architecture for on-chip networks.
J. Syst. Archit.
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2012 B conf
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS.
FPL
Antoni Roca, José Flich, Giorgos Dimitrakopoulos
2012 B conf
Enabling High-Performance Crossbars through a Floorplan-Aware Design.
ICPP
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2012 J jnl
On the Impact of Within-Die Process Variation in GALS-Based NoC Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato
2011 B conf
A Distributed Switch Architecture for On-Chip Networks.
ICPP
Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2011 J jnl
A low-latency modular switch for CMP systems.
Microprocess. Microsystems
Antoni Roca, José Flich, Federico Silla, José Duato
2011 J jnl
Characterizing the impact of process variation on 45 nm NoC-based CMPs.
J. Parallel Distributed Comput.
Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
2011 J jnl
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato
2011 J jnl
Fault-Tolerant Vertical Link Design for Effective 3D Stacking.
IEEE Comput. Archit. Lett.
Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
2011 B conf
PC-Mesh: A Dynamic Parallel Concentrated Mesh.
ICPP
Jesús Camacho Villanueva, José Flich, Antoni Roca, José Duato
2010 C conf
A Latency-Efficient Router Architecture for CMP Systems.
DSD
Antoni Roca, José Flich, Federico Silla, José Duato
2010 — conf
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.
NOCS
Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato
2010 — conf
Improving the Performance of GALS-Based NoCs in the Presence of Process Variation.
NOCS
Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato
2010 Misc conf
VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks.
HiPC
Antoni Roca, José Flich, Federico Silla, José Duato