Anton Tsertov

21 papers A 2B 1C 5Journal 1Unranked 11
YearRankTypeTitle / Venue / Authors
2024 — conf
Keynote: Cost-Efficient Reliability for Edge-AI Chips.
LATS
Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab
2024 — conf
Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs.
DFT
Hardi Selg, Konstantin Shibin, Anton Tsertov, Maksim Jenihhin, Peeter Ellervee, Jaan Raik
2023 — conf
On-Chip Sensors Data Collection and Analysis for SoC Health Management.
DFT
Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
2023 J jnl
On-Chip Sensors Data Collection and Analysis for SoC Health Management.
CoRR
Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
2019 B conf
Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks.
ETS
Aleksa Damljanovic, Artur Jutman, Giovanni Squillero, Anton Tsertov
2019 A conf
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL.
ITC
Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez, Giovanni Squillero, Anton Tsertov
2017 — conf
Automated software-based self-test generation for microprocessors.
MIXDES
Artjom Jasnetski, Raimund Ubar, Anton Tsertov
2017 — conf
High-level test data generation for software-based self-test in microprocessors.
MECO
Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar
2017 — ed.
VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers
VLSI-SoC (Selected Papers)
Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis
2016 A conf
A suite of IEEE 1687 benchmark networks.
ITC
Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath
2016 C conf
FPGA-controlled PCBA power-on self-test using processor's debug features.
DDECS
Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Julio Pérez Acle, Anton Tsertov
2016 C conf
High-level modeling and testing of multiple control faults in digital systems.
DDECS
Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schölzel, Raimund Ubar
2016 — conf
On automatic software-based self-test program generation based on high-level decision diagrams.
LATS
Artjom Jasnetski, Raimund Ubar, Anton Tsertov
2015 C conf
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams.
DDECS
Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
2014 — conf
Laboratory framework TEAM for investigating the dependability issues of microprocessor systems.
EWME
Artjom Jasnetski, Raimund Ubar, Anton Tsertov, Helena Kruus
2014 — conf
Software-based self-test generation for microprocessors with high-level decision diagrams.
LATW
Raimund Ubar, Anton Tsertov, Artjom Jasnetski, Marina Brik
2013 — conf
On in-system programming of non-volatile memories.
MIXDES
Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski
2011 — conf
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models.
Asian Test Symposium
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
2011 C conf
SoC and Board Modeling for Processor-Centric Board Testing.
DSD
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
2010 — conf
Testing beyond the SoCs in a lego style.
EWDTS
Anton Tsertov, Artur Jutman, Sergei Devadze
2008 C conf
Calculation of LFSR Seed and Polynomial Pair for BIST Applications.
DDECS
Artur Jutman, Anton Tsertov, Raimund Ubar