Anthony Chan Carusone

106 papers A 1C 12Journal 53Unranked 40

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Time-Domain Dual-Edge Asynchronous Pipelined SAR ADC Featuring Reset-Free Quantization at Multi-GS/s. CoRR Richard Zeng, Anthony Chan Carusone, Xilin Liu
2025	J	`jnl`	An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI. IEEE Open J. Circuits Syst. Bangda Yang, Trevor C. Caldwell, Anthony Chan Carusone
2025	J	`jnl`	An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems. IEEE Trans. Circuits Syst. II Express Briefs Richard Barrie, Ming Yang, Hossein Shakiba, Anthony Chan Carusone
2025	J	`jnl`	Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications. IEEE Open J. Circuits Syst. Kunal Yadav, Ping-Hsuan Hsieh, Anthony Chan Carusone
2024	—	`conf`	An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems. MWSCAS Richard Barrie, Ming Yang, Hossein Shakiba, Anthony Chan Carusone
2024	J	`jnl`	An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning - From Specifications to Layouts. IEEE Access Zonghao Li, Anthony Chan Carusone
2024	C	`conf`	Design of a Linearized Power-Efficient Dynamic Amplifier in 22nm FDSOI. ISCAS Bangda Bender Yang, Anthony Chan Carusone
2023	A	`conf`	Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process. ICCAD Zonghao Li, Anthony Chan Carusone
2022	—	`conf`	A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes. CICC Dhruv Patel, Alireza Sharif Bakhtiar, Anthony Chan Carusone
2022	J	`jnl`	Estimation of Broadband Time-Interleaved ADC's Impairments and Performance Using Only Single-Tone Measurements. IEEE Access Hong Zhang, Ahmad Hassan, Paul Chen, W. Martin Snelgrove, Anthony Chan Carusone
2022	J	`jnl`	Loop Dynamics Analysis of PAM-4 Mueller-Muller Clock and Data Recovery System. IEEE Open J. Circuits Syst. Kunal Yadav, Ping-Hsuan Hsieh, Anthony Chan Carusone
2022	J	`jnl`	Spectrally Efficient DMT Operation With BER-Informed Dynamic Bit and Power Loading. IEEE Access Behraz Vatankhahghadim, Bahaa Radi, Masum Hossain, Anthony Chan Carusone
2021	J	`jnl`	A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s. IEEE Open J. Circuits Syst. Behraz Vatankhahghadim, Nijwm Wary, James Bailey, Anthony Chan Carusone
2021	J	`jnl`	Peak-SNR Analysis of CMOS TDCs for SPAD-Based TCSPC 3D Imaging Applications. IEEE Trans. Circuits Syst. II Express Briefs Foad Arvani, Anthony Chan Carusone
2021	C	`conf`	Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. ISCAS Ming Yang, Shayan Shahramian, Henry Wong, Peter Krotnev, Anthony Chan Carusone
2020	C	`conf`	All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs. ISCAS Paul Wenbo Chen, Nijwm Wary, Luke Wang, QiWei Wang, Anthony Chan Carusone
2020	—	`conf`	An Adaptive Spatial Blocker Cancellation Receiver for Multiple Antenna Systems. NEWCAS Rudraneil Saha, Anthony Chan Carusone
2020	C	`conf`	Discrete Multitone Signalling for Wireline Communication. ISCAS Behraz Vatankhahghadim, Nijwm Wary, Anthony Chan Carusone
2020	J	`jnl`	Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. IEEE Trans. Circuits Syst. I Regul. Pap. Ming Yang, Shayan Shahramian, Hossein Shakiba, Henry Wong, Peter Krotnev, Anthony Chan Carusone
2019	—	`conf`	A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto
2019	J	`jnl`	A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET. IEEE J. Solid State Circuits Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone
2018	—	`conf`	A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET. ISSCC Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone
2018	J	`jnl`	A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers. IEEE J. Solid State Circuits QiWei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone
2018	J	`jnl`	A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing. IEEE Trans. Very Large Scale Integr. Syst. Hong Zhang, Junqiang Sun, Jie Zhang, Ruizhi Zhang, Anthony Chan Carusone
2018	J	`jnl`	A Nano-Watt MOS-Only Voltage Reference With High-Slope PTAT Voltage Generators. IEEE Trans. Circuits Syst. II Express Briefs Hong Zhang, Xipeng Liu, Jie Zhang, Hongshuai Zhang, Jijun Li, Ruizhi Zhang, Shuai Chen, Anthony Chan Carusone
2018	J	`jnl`	A Sub-mW Integrating Mixer SAR Spectrum Sensor for Portable Cognitive Radio Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Kevin Banovic, Anthony Chan Carusone
2017	J	`jnl`	A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET. IEEE Trans. Circuits Syst. II Express Briefs Luke Wang, Marc-Andre LaCroix, Anthony Chan Carusone
2017	—	`conf`	A 40-Gbps 0.5-pJ/bit VCSEL driver in 28nm CMOS with complex zero equalizer. CICC Alireza Sharif Bakhtiar, Michael G. Lee, Anthony Chan Carusone
2017	—	`conf`	A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS. CICC QiWei Wang, Hajime Shibata, Anthony Chan Carusone, Antonio Liscidini
2017	J	`jnl`	All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Very Large Scale Integr. Syst. Shuai Chen, Luke Wang, Hong Zhang, Rosanah Murugesu, Dustin Dunwell, Anthony Chan Carusone
2017	—	`conf`	Filtering ADCs for wireless receivers: A survey. MWSCAS QiWei Wang, Antonio Liscidini, Anthony Chan Carusone
2017	—	`conf`	Low-power CMOS receivers for short reach optical communication. CICC Alireza Sharif Bakhtiar, Michael G. Lee, Anthony Chan Carusone
2016	—	`conf`	23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs. ISSCC Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
2016	J	`jnl`	A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication. IEEE J. Solid State Circuits Behzad Dehlaghi, Anthony Chan Carusone
2016	J	`jnl`	A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE. IEEE J. Solid State Circuits Alireza Sharif Bakhtiar, Anthony Chan Carusone
2016	J	`jnl`	Capacitively-Coupled CMOS VCSEL Driver Circuits. IEEE J. Solid State Circuits Victor Kozlov, Anthony Chan Carusone
2016	J	`jnl`	Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs. IEEE J. Solid State Circuits Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone
2015	J	`jnl`	A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS. IEEE J. Solid State Circuits Shayan Shahramian, Anthony Chan Carusone
2015	—	`conf`	A 19.6-Gbps CMOS optical receiver with local feedback IIR DFE. VLSIC Alireza Sharif Bakhtiar, Anthony Chan Carusone
2015	—	`conf`	A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS. CICC Behzad Dehlaghi, Anthony Chan Carusone
2015	—	`conf`	A 26-Gb/s 1.80-pJ/b CMOS-driven transmitter for 850-nm common-cathode VCSELs. OFC M. Shibata, Anthony Chan Carusone
2015	J	`jnl`	Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS". IEEE J. Solid State Circuits Shayan Shahramian, Anthony Chan Carusone
2015	—	`conf`	Cycle-slipping pull-in range of bang-bang PLLs. NEWCAS Amer Samarah, Anthony Chan Carusone
2015	C	`conf`	Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition. ISCAS Amer Samarah, Anthony Chan Carusone
2014	—	`conf`	A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS. ESSCIRC Shayan Shahramian, Anthony Chan Carusone
2014	C	`conf`	A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC. ISCAS Mike Bichan, Dustin Dunwell, QiWei Wang, Anthony Chan Carusone
2014	—	`conf`	Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS. ESSCIRC Luke Wang, QiWei Wang, Anthony Chan Carusone
2013	J	`jnl`	A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC. IEEE J. Solid State Circuits Amer Samarah, Anthony Chan Carusone
2013	C	`conf`	Channel characterization using jitter measurements. ISCAS Dustin Dunwell, Atul Gupta, Anthony Chan Carusone
2013	J	`jnl`	Modeling Oscillator Injection Locking Using the Phase Domain Response. IEEE Trans. Circuits Syst. I Regul. Pap. Dustin Dunwell, Anthony Chan Carusone
2012	J	`jnl`	A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs. IEEE J. Solid State Circuits Kentaro Yamamoto, Anthony Chan Carusone
2012	—	`conf`	A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. CICC Dustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble
2012	—	`conf`	A dead-zone free and linearized digital PLL. ICECS Amer Samarah, Anthony Chan Carusone
2012	—	`conf`	A digital phase-locked loop with calibrated coarse and stochastic fine TDC. CICC Amer Samarah, Anthony Chan Carusone
2012	J	`jnl`	Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters. IEEE Trans. Circuits Syst. II Express Briefs Shayan Shahramian, Hemesh Yasotharan, Anthony Chan Carusone
2011	J	`jnl`	7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS. IEEE J. Solid State Circuits Masum Hossain, Anthony Chan Carusone
2011	—	`conf`	A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs. CICC Kentaro Yamamoto, Anthony Chan Carusone
2011	J	`jnl`	CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors. IEEE J. Solid State Circuits Anthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao
2011	J	`jnl`	Design of a Dual W- and D-Band PLL. IEEE J. Solid State Circuits Shahriar Shahramian, Adam Hart, Alexander Tomkins, Anthony Chan Carusone, Patrice Garcia, Pascal Chevalier, Sorin P. Voinigescu
2010	J	`jnl`	5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS. IEEE J. Solid State Circuits Masum Hossain, Anthony Chan Carusone
2010	C	`conf`	A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS. ISCAS Dustin Dunwell, Anthony Chan Carusone
2010	J	`jnl`	A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. Tony Shuo-Chun Kao, Faisal A. Musa, Anthony Chan Carusone
2010	—	`conf`	A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS. ISSCC Masum Hossain, Anthony Chan Carusone
2010	—	`conf`	Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver. CICC Dustin Dunwell, Anthony Chan Carusone
2010	J	`jnl`	Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels. IEEE Trans. Circuits Syst. I Regul. Pap. Masum Hossain, Anthony Chan Carusone
2010	—	`conf`	Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectors. CICC Anthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao
2009	J	`jnl`	A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology. IEEE Trans. Circuits Syst. I Regul. Pap. Anthony Chan Carusone, Horace Cheng, Faisal A. Musa
2009	J	`jnl`	A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees. IEEE J. Solid State Circuits Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone
2009	C	`conf`	An Anti-aliasing Multi-rate SigmaDelta Modulator. ISCAS Anthony Chan Carusone, Franco Maloberti
2009	J	`jnl`	CMOS Oscillators for Clock Distribution and Injection-Locked Deskew. IEEE J. Solid State Circuits Masum Hossain, Anthony Chan Carusone
2009	J	`jnl`	Guest Editorial Special Issue on ISCAS 2008. IEEE Trans. Circuits Syst. I Regul. Pap. Anthony Chan Carusone, Yehea Ismail, Un-Ku Moon, Hanspeter Schmid, Wouter A. Serdijn, Gianluca Setti
2009	J	`jnl`	Introducing Jump-Start Tutorials. IEEE Trans. Circuits Syst. II Express Briefs Anthony Chan Carusone, Un-Ku Moon
2009	J	`jnl`	Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference. IEEE J. Solid State Circuits Lawrence T. Clark, Anthony Chan Carusone, Payam Heydari
2008	—	`conf`	20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS. CICC Masum Hossain, Anthony Chan Carusone
2008	—	`conf`	A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS. CICC Horace Cheng, Anthony Chan Carusone
2008	—	`conf`	A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing. CICC Mike Bichan, Anthony Chan Carusone
2008	J	`jnl`	A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR. IEEE J. Solid State Circuits Kentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson
2008	J	`jnl`	A Time-Interleaved DeltaSigma-DAC Architecture Clocked at the Nyquist Rate. IEEE Trans. Circuits Syst. II Express Briefs Jennifer Pham, Anthony Chan Carusone
2008	C	`conf`	A passive filter aided timing recovery scheme. ISCAS Faisal A. Musa, Anthony Chan Carusone
2008	J	`jnl`	Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity. IEEE Trans. Circuits Syst. II Express Briefs Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang
2008	—	`conf`	High-performance chip-to-chip signaling. ICECS Anthony Chan Carusone
2008	J	`jnl`	Power Reduction Techniques for LDPC Decoders. IEEE J. Solid State Circuits Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang
2007	—	`conf`	A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. CICC Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang
2007	—	`conf`	A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR. CICC Kentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson
2007	C	`conf`	Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links. ISCAS Mike Bichan, Anthony Chan Carusone
2007	J	`jnl`	Editorial ISCAS 2006 Special Section on Analog Circuits and Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Tuna B. Tarim, Anthony Chan Carusone
2007	J	`jnl`	Modeling and Design of Multilevel Bang-Bang CDRs in the Presence of ISI and Noise. IEEE Trans. Circuits Syst. I Regul. Pap. Faisal A. Musa, Anthony Chan Carusone
2006	J	`jnl`	A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology. IEEE J. Solid State Circuits Adesh Garg, Anthony Chan Carusone, Sorin P. Voinigescu
2006	—	`conf`	A 19-GHz Broadband Amplifier Using a g CICC Masum Hossain, Anthony Chan Carusone
2006	J	`jnl`	A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-$mu$m CMOS. IEEE J. Solid State Circuits Jonathan Sewter, Anthony Chan Carusone
2006	—	`conf`	A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology. CICC Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone
2006	J	`jnl`	A Baud-Rate Timing Recovery Scheme With a Dual-Function Analog Filter. IEEE Trans. Circuits Syst. II Express Briefs Faisal A. Musa, Anthony Chan Carusone
2006	J	`jnl`	A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s. IEEE J. Solid State Circuits Jonathan Sewter, Anthony Chan Carusone
2006	C	`conf`	A bit-serial approximate min-sum LDPC decoder and FPGA implementation. ISCAS Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang
2006	J	`jnl`	An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers. IEEE Trans. Circuits Syst. II Express Briefs Anthony Chan Carusone
2006	J	`jnl`	Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology. IEEE J. Solid State Circuits Shahriar Shahramian, Anthony Chan Carusone, Sorin P. Voinigescu
2005	—	`conf`	A 40 Gb/s transversal filter in 0.18 μm CMOS using distributed amplifiers. CICC Jonathan Sewter, Anthony Chan Carusone
2005	—	`conf`	A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems. ISCAS (2) Jonathan Sewter, Anthony Chan Carusone
2005	—	`conf`	Jitter equalization for binary baseband communication. ISCAS (2) Anthony Chan Carusone
2005	—	`conf`	Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity. ISCAS (5) Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang
2003	—	`conf`	A sigma-delta based open-loop frequency modulator. ISCAS (1) Denis Daly, Anthony Chan Carusone
2003	—	`conf`	Clock recovery in high-speed multilevel serial links. ISCAS (5) Faisal A. Musa, Anthony Chan Carusone
2003	J	`jnl`	Digital LMS adaptation of analog filters without gradient information. IEEE Trans. Circuits Syst. II Express Briefs Anthony Chan Carusone, David A. Johns
2002	—	`conf`	A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes. ISCAS (4) Anthony Chan Carusone, David A. Johns
2002	—	`conf`	Analog filter adaptation using a dithered linear search algorithm. ISCAS (4) Anthony Chan Carusone, David A. Johns
1999	—	`conf`	Obtaining digital gradient signals for analog adaptive filters. ISCAS (3) Anthony Chan Carusone, David A. Johns