Anshul Kumar

109 papers A* 4A 5B 5C 8Misc 41Journal 29Unranked 17
YearRankTypeTitle / Venue / Authors
2026 J jnl
Is Sanskrit the most token-efficient language? A quantitative study using GPT, Gemini, and SentencePiece.
CoRR
Anshul Kumar
2025 J jnl
AdaGradSelect: An adaptive gradient-guided layer selection method for efficient fine-tuning of SLMs.
CoRR
Anshul Kumar, Gagan Raj Gupta, Manisha Chawla
2025 — conf
Flex-GAD : Flexible Graph Anomaly Detection.
CODS
Apu Chakraborty, Anshul Kumar, Gagan Raj Gupta
2025 J jnl
Flex-GAD : Flexible Graph Anomaly Detection.
CoRR
Apu Chakraborty, Anshul Kumar, Gagan Raj Gupta
2025 J jnl
MM-Telco: Benchmarks and Multimodal Large Language Models for Telecom Applications.
CoRR
Gagan Raj Gupta, Anshul Kumar, Manish Rai, Apu Chakraborty, Ashutosh Modi, Abdelaali Chaoub, Soumajit Pramanik, Moyank Giri, Yashwanth Holla, Sunny Kumar, M. V. Kiran Sooraj
2024 — conf
Dynamic Load Balancing for Enhanced Resource Utilization in IaaS Cloud Computing.
IC3I
Anshul Kumar, Sandeep Mathur, Adarsh Malviya
2024 — conf
What does your Packet Capture say?
COMAD/CODS (December)
Anshul Kumar, Gagan Raj Gupta, Sunny Kumar, Ankita Sahu, Apu Chakraborty
2023 J jnl
A survey on emotion-cause extraction in psychological text using deep learning methods.
Prog. Artif. Intell.
Anshul Kumar, Ankit Kumar Jain
2023 J jnl
Cost Optimization of an Unreliable server queue with two stage service process under hybrid vacation policy.
Math. Comput. Simul.
Anshul Kumar, Madhu Jain
2022 J jnl
Effect of disaster and balking on M/M/1 driven fluid queue with working vacation.
Int. J. Math. Oper. Res.
Madhu Jain, Anshul Kumar
2022 J jnl
Emotion detection in psychological texts by fine-tuning BERT using emotion-cause pair extraction.
Int. J. Speech Technol.
Anshul Kumar, Ankit Kumar Jain
2022 J jnl
Game Theory-Based Parameter Tuning for Energy-Efficient Path Planning on Modern UAVs.
ACM Trans. Cyber Phys. Syst.
Diksha Moolchandani, Kishore Yadav, Geesara Kulathunga, Ilya Afanasyev, Anshul Kumar, Manuel Mazzara, Smruti Sarangi
2022 J jnl
Minimizing Off-Chip Memory Access for CNN Accelerators.
IEEE Consumer Electron. Mag.
Saurabh Tewari, Anshul Kumar, Kolin Paul
2022 J jnl
Performance and Power Prediction for Concurrent Execution on GPUs.
ACM Trans. Archit. Code Optim.
Diksha Moolchandani, Anshul Kumar, Smruti R. Sarangi
2022 A conf
PredStereo: An Accurate Real-time Stereo Vision System.
WACV
Diksha Moolchandani, Nivedita Shrivastava, Anshul Kumar, Smruti R. Sarangi
2022 A conf
SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators.
DATE
Saurabh Tewari, Anshul Kumar, Kolin Paul
2021 J jnl
Accelerating CNN Inference on ASICs: A Survey.
J. Syst. Archit.
Diksha Moolchandani, Anshul Kumar, Smruti R. Sarangi
2021 Misc conf
Game Theory-Based Parameter-Tuning for Path Planning of UAVs.
VLSID
Diksha Moolchandani, Geesara Prathap, Ilya Afanasyev, Anshul Kumar, Manuel Mazzara, Smruti R. Sarangi
2021 J jnl
Performance-Energy Trade-off in Modern CMPs.
ACM Trans. Archit. Code Optim.
Solomon Abera, M. Balakrishnan, Anshul Kumar
2021 J jnl
The application of predictive analytics to identify at-risk students in health professions education.
CoRR
Anshul Kumar, Roger Edwards, Lisa Walker
2020 — conf
Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators.
ISVLSI
Saurabh Tewari, Anshul Kumar, Kolin Paul
2020 B conf
Performance Prediction for Multi-Application Concurrency on GPUs.
ISPASS
Diksha Moolchandani, Sudhanshu Gupta, Anshul Kumar, Smruti R. Sarangi
2020 J jnl
VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Diksha Moolchandani, Anshul Kumar, José F. Martínez, Smruti R. Sarangi
2019 — conf
ML Guided Energy-Performance Trade-Off Estimation For Uncore Frequency Scaling.
SpringSim
Solomon Abera Bekele, M. Balakrishnan, Anshul Kumar
2018 — conf
Performance-Energy Trade-off in CMPs with Per-Core DVFS.
ARCS
Solomon Abera, M. Balakrishnan, Anshul Kumar
2017 — conf
PLSS: A Scheduler for Multi-core Embedded Systems.
ARCS
Solomon Abera, M. Balakrishnan, Anshul Kumar
2016 Misc conf
Impact of crosstalk and process variation on capture power reduction for at-speed test.
VTS
Surya Piplani, G. S. Visweswaran, Anshul Kumar
2014 J jnl
Shared-port register file architecture for low-energy VLIW processors.
ACM Trans. Archit. Code Optim.
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
2013 C conf
High performance 3D-FFT implementation.
ISCAS
U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar
2012 J jnl
Exploiting UML based validation for compliance checking of TLM 2 based models.
Des. Autom. Embed. Syst.
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
2011 B conf
A SysML Profile for Development and Early Validation of TLM 2.0 Models.
ECMFA
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
2011 C conf
A UML based framework for efficient validation of TLM 2 models.
FDL
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
2011 Misc conf
Exploiting temporal decoupling to accelerate trace-driven NoC emulation.
CODES+ISSS
Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar
2011 C conf
Strap-down Pedestrian Dead-Reckoning system.
IPIN
Pragun Goyal, Vinay J. Ribeiro, Huzur Saran, Anshul Kumar
2010 — conf
A high-level synthesis flow for custom instruction set extensions for application-specific processors.
ASP-DAC
Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul
2010 Misc conf
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation.
CODES+ISSS
Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar
2010 Misc conf
Front-End Design Flows for Systems on Chip: An Embedded Tutorial.
VLSI Design
Anshul Kumar, Preeti Ranjan Panda
2010 Misc conf
Instruction Selection in ASIP Synthesis Using Functional Matching.
VLSI Design
Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar
2009 Misc conf
An Index-Based Mobile Checkpointing and Recovery Algorithm.
ICDCN
Awadhesh Kumar Singh, Rohit Bhat, Anshul Kumar
2008 Misc conf
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.
VLSI Design
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2008 Misc conf
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.
VLSI Design
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2007 Misc conf
Application Specific Datapath Extension with Distributed I/O Functional Units.
VLSI Design
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2007 J jnl
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
Int. J. Parallel Program.
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
2007 J jnl
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.
ACM Trans. Design Autom. Electr. Syst.
Anup Gangwar, M. Balakrishnan, Anshul Kumar
2007 Misc conf
Power Reduction in VLIW Processor with Compiler Driven Bypass Network.
VLSI Design
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
2007 — conf
Recurring Pattern Identification and its Application to Instruction Set Extension.
CDES
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2006 A conf
Battery aware dynamic scheduling for periodic task graphs.
IPDPS
Venkat Rao, Nicolas Navet, Gaurav Singhal, Anshul Kumar, G. S. Visweswaran
2006 C conf
Rapid Resource-Constrained Hardware Performance Estimation.
IEEE International Workshop on Rapid System Prototyping
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar
2005 Misc conf
Battery Model for Embedded Systems.
VLSI Design
Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas Navet
2005 A conf
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
DATE
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
2005 Misc conf
Integrated On-Chip Storage Evaluation in ASIP Synthesis.
VLSI Design
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2004 J jnl
An efficient technique for exploring register file size in ASIP design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2004 Misc conf
Automatic synthesis of system on chip multiprocessor architectures for process networks.
CODES+ISSS
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
2004 C conf
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.
SCOPES
Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne
2004 Misc conf
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture.
VLSI Design
Sourabh Saluja, Anshul Kumar
2004 Misc conf
Real Time Dynamic Voltage Scaling For Embedded Systems.
VLSI Design
Venkat Rao, Gaurav Singhal, Anshul Kumar
2004 Misc conf
Synthesis of Application Specific Multiprocessor Architectures for Process Networks.
VLSI Design
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
2003 Misc conf
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.
VLSI Design
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar
2003 C conf
Exploring Storage Organization in ASIP Synthesis.
DSD
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2003 J jnl
Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing.
Des. Autom. Embed. Syst.
Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
2003 Misc conf
SoC Synthesis with Automatic Hardware Software Interface Generation.
VLSI Design
Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar
2002 — conf
A New Divide and Conquer Method for Achieving High Speed Division in Hardware.
ASP-DAC/VLSI Design
Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
2002 — conf
A New Performance Evaluation Approach for System Level Design Space Exploration.
ISSS
M. Balakrishnan, Anshul Kumar, C. P. Joshi
2002 — conf
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.
ISSS
M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
2002 Misc conf
An efficient technique for exploring register file size in ASIP synthesis.
CASES
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2002 — conf
Exploring the Number of Register Windows in ASIP Synthesis.
ASP-DAC/VLSI Design
Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar
2002 C conf
Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing.
IEEE International Workshop on Rapid System Prototyping
Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
2002 — conf
Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards.
FPT
Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
2001 Misc conf
ASIP Design Methodologies : Survey and Issues.
VLSI Design
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
2001 Misc conf
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study.
VLSI Design
Anupam Rastogi, M. Balakrishnan, Anshul Kumar
2001 Misc conf
Synthesizing A Long Latency Unit Within Vliw Processor.
VLSI Design
Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busá
2000 J jnl
A scheme for multiple on-chip signature checking for embedded SRAMS.
J. Syst. Archit.
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
2000 B conf
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.
FPL
Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
2000 Misc conf
Evaluation of Various Routing Architectures for Multi-FPGA Boards.
VLSI Design
Sushil Chandra Jain, Shashi Kumar, Anshul Kumar
2000 J jnl
Grammar-based hardware synthesis from port-size independent specifications.
IEEE Trans. Very Large Scale Integr. Syst.
Johnny Öberg, Anshul Kumar, Ahmed Hemani
2000 Misc conf
nterface Synthesis: Issues and Approaches.
VLSI Design
Arvind Rajawat, M. Balakrishnan, Anshul Kumar
1999 J jnl
Built-in Self Test Based on Multiple On-Chip Signature Checking.
J. Electron. Test.
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998 Misc conf
An Object-Oriented Concept for Intelligent Library Functions.
VLSI Design
Johnny Öberg, Axel Jantsch, Anshul Kumar
1998 J jnl
Direct mapping of RTL structures onto LUT-based FPGA's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1998 Misc conf
Hybrid Testing Schemes Based on Mutual and Signature Testing.
VLSI Design
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998 Misc conf
On-Chip Signature Checking for Embedded Memories.
VLSI Design
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998 J jnl
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.
J. Electron. Test.
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1998 A conf
Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols.
DATE
Johnny Öberg, Ahmed Hemani, Anshul Kumar
1998 — conf
Specification of Exception Handling in Grammar-Based Hardware Synthesis.
EUROMICRO
Johnny Öberg, Anshul Kumar, Ahmed Hemani
1998 Misc conf
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.
VLSI Design
Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar
1997 — conf
A scheme for multiple on-chip signature checking for embedded SRAMs.
ED&TC
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1997 Misc conf
Efficient Implementation of Multiple On-Chip Signature Checking.
VLSI Design
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1997 Misc conf
Optimal Clock Period for Synthesized Data Paths.
VLSI Design
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1996 Misc conf
A Novel BIST Architecture With Built-in Self Check.
VLSI Design
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
1996 Misc conf
A multiplier generator for Xilinx FPGAs.
VLSI Design
Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar
1996 — conf
Grammar-Based Hardware Synthesis of Data Communication Protocols.
ISSS
Johnny Öberg, Anshul Kumar, Ahmed Hemani
1995 Misc conf
An HOL based framework for design of correct high level synthesizers.
VLSI Design
B. M. Subraya, Anshul Kumar, Shashi Kumar
1995 C conf
Circuit partitioning with partial order for mixed simulation emulation environment.
RSP
Gurmeet Singh Manku, Anshul Kumar, Shashi Kumar
1995 B conf
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs.
FPL
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1995 Misc conf
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.
VLSI Design
Alok Kumar, Anshul Kumar, M. Balakrishnan
1994 B conf
An Efficient Technique for Mapping RTL Structures onto FPGAs.
FPL
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1994 Misc conf
FAST: FPGA Targeted RTL Structure Synthesis Technique.
VLSI Design
A. R. Naseer, M. Balakrishnan, Anshul Kumar
1993 Misc conf
DESSERT: Design Space Exploration of RT Level Components.
VLSI Design
M. V. Rao, M. Balakrishnan, Anshul Kumar
1993 Misc conf
High Level Design Experiences with IDEAS.
VLSI Design
C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer
1992 Misc conf
A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas.
VLSI Design
Manu Lauria, Shashi Kumar, Anshul Kumar
1992 Misc conf
Data Path Synthesis With Global Time Constraint.
VLSI Design
Prashant P. Nedungadi, M. Balakrishnan, Anshul Kumar
1989 A* conf
Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions.
DAC
Anshul Kumar, Shashi Kumar, P. Kulshreshtha, Sudipto Ghose
1989 J jnl
Ideas: a tool for VLSI CAD.
IEEE Des. Test
Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar
1986 J jnl
Automatic Generation of Digital System Schematic Diagrams.
IEEE Des. Test
Anshul Kumar, Anjali Arya, V. V. Swaminathan, Amit Misra
1985 A* conf
An automated data path synthesizer for a canonic structure, implementable in VLSI.
DAC
Kumar Ramayya, Anshul Kumar, Surendra Prasad
1985 A* conf
Automatic generation of digital system schematic diagrams.
DAC
Anjali Arya, Anshul Kumar, V. V. Swaminathan, Amit Misra
1984 Misc conf
Recognition of consonants using an ARMA model of the speech signal.
ICASSP
Anshul Kumar, George A. Bekey
1983 J jnl
A methodology for custom VLSI layout.
IEEE Trans. Syst. Man Cybern.
Melvin A. Breuer, Anshul Kumar
1980 A* conf
A Structured Language for CAD of Digital Systems.
ISCA
Anshul Kumar, P. C. P. Bhatt