Anni Lu

29 papers A* 2A 1B 2C 1Journal 16Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
16 Arrays of 32 All-to-All Coupled CMOS Oscillators for AI Inference and Combinatorial Optimization.
CICC
Hai Li, James S. Ayers, Anni Lu, You Li, Dmitri E. Nikonov, Yongping Fan, Ian A. Young
2025 C conf
Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems.
ISCAS
Yuyao Kong, Jianwei Jia, Anni Lu, Faaiq G. Waqar, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu
2025 A* conf
Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories.
DAC
Faaiq Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu
2025 J jnl
Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories.
CoRR
Faaiq G. Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu
2025 J jnl
NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities.
CoRR
James Read, Ming-Yen Lee, Wei-Hsing Huang, Yuan-Chun Luo, Anni Lu, Shimeng Yu
2024 B conf
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators.
ASPDAC
Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu
2024 J jnl
A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Po-Kai Hsu, Vaidehi Garg, Anni Lu, Shimeng Yu
2024 — —
Algorithm-Hardware Co-design for Deep Learning and Probabilistic Computing with Compute-in-Memory Accelerators.
Anni Lu
2024 A* conf
Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization.
DAC
Anni Lu, Junmo Lee, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu
2024 J jnl
Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Chun Luo, Anni Lu, Yandong Luo, Sou-Chi Chang, Uygar Avci, Shimeng Yu
2024 J jnl
NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junmo Lee, Anni Lu, Wantong Li, Shimeng Yu
2024 J jnl
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Chun Luo, Anni Lu, Janak Sharda, Moritz Scherer, Jorge Tomás Gómez, Syed Shakib Sarwar, Ziyun Li, Reid Frederick Pinkham, Barbara De Salvo, Shimeng Yu
2023 B conf
CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators.
IJCNN
Minah Lee, Anni Lu, Mandovi Mukherjee, Shimeng Yu, Saibal Mukhopadhyay
2023 J jnl
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Anni Lu, Jae Hur, Yuan-Chun Luo, Hai Li, Dmitri E. Nikonov, Ian A. Young, Yang-Kyu Choi, Shimeng Yu
2022 J jnl
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
2022 — conf
Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling.
VLSI Technology and Circuits
Gihun Choe, Prasanna Venkatesan Ravindran, Anni Lu, Jae Hur, Maximilian Lederer, André Reck, Sarah Lombardo, Nashrah Afroze, Josh Kacher, Asif Islam Khan, Shimeng Yu
2022 J jnl
Nonvolatile Capacitive Crossbar Array for In-Memory Computing.
Adv. Intell. Syst.
Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu
2022 J jnl
Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saurabh Dash, Yandong Luo, Anni Lu, Shimeng Yu, Saibal Mukhopadhyay
2021 A conf
A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator.
DATE
Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
2021 J jnl
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference.
ACM Trans. Design Autom. Electr. Syst.
Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
2021 — conf
Compute-in-Memory: From Device Innovation to 3D System Integration.
ESSDERC
Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-Chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng
2021 — conf
Compute-in-RRAM with Limited On-chip Resources.
AICAS
Anni Lu, Xiaochen Peng, Shimeng Yu
2021 J jnl
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
2021 — conf
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing.
IMW
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
2021 J jnl
Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Beomseok Kang, Anni Lu, Yun Long, Daehyun Kim, Shimeng Yu, Saibal Mukhopadhyay
2021 J jnl
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.
Frontiers Artif. Intell.
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 — conf
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro.
AICAS
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2020 J jnl
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint.
IEEE Trans. Very Large Scale Integr. Syst.
Anni Lu, Xiaochen Peng, Yandong Luo, Shimeng Yu
2020 J jnl
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training.
CoRR
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu