Anne-Johan Annema

47 papers C 3Journal 23Unranked 20

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	A Single-Trim Frequency Reference System With 0.7 ppm/°C From -63 °C to 165 °C Consuming 210 μW at 70 MHz. IEEE J. Solid State Circuits Alexander S. Delke, Thomas J. Hoen, Anne-Johan Annema, Yanyu Jin, Jos Verlinden, Bram Nauta
2022	J	`jnl`	Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. IEEE Trans. Circuits Syst. I Regul. Pap. Maikel Huiskamp, Mark S. Oude Alink, Bram Nauta, Anne-Johan Annema, Harijot Singh Bindra
2021	J	`jnl`	A Single-Trim Frequency Reference Achieving ±120 ppm Accuracy From -50 °C to 170 °C. IEEE J. Solid State Circuits Alexander S. Delke, Anne-Johan Annema, Mark S. Oude Alink, Yanyu Jin, Jos Verlinden, Bram Nauta
2020	—	`conf`	A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C. CICC Alexander S. Delke, Anne-Johan Annema, Mark S. Oude Alink, Yanyu Jin, Jos Verlinden, Bram Nauta
2020	J	`jnl`	Theory and Implementation of a Load-Mismatch Protective Class-E PA System. IEEE Trans. Circuits Syst. I Regul. Pap. Jeroen Ponte, Ali Ghahremani, Maikel Huiskamp, Anne-Johan Annema, Bram Nauta
2019	J	`jnl`	A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements. IEEE Trans. Circuits Syst. II Express Briefs Ali Ghahremani, Anne-Johan Annema, Bram Nauta
2019	—	`conf`	A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. VLSI Circuits Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta
2019	—	`conf`	A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. CICC Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta, Simon M. Louwsma
2018	J	`jnl`	A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. IEEE J. Solid State Circuits Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta
2018	J	`jnl`	A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs Maikel Huiskamp, Anne-Johan Annema, Bram Nauta
2018	—	`conf`	Augmentation of Class-E PA Reliability under Load Mismatch Conditions. ICECS Jeroen Ponte, Ali Ghahremani, Maikel Huiskamp, Anne-Johan Annema, Bram Nauta
2018	J	`jnl`	Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement. IEEE J. Solid State Circuits Ali Ghahremani, Anne-Johan Annema, Bram Nauta
2017	—	`conf`	A 30fJ/comparison dynamic bias comparator. ESSCIRC Harijot Singh Bindra, Chris E. Lokin, Anne-Johan Annema, Bram Nauta
2017	—	`conf`	An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. ESSCIRC Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta
2017	J	`jnl`	Hardware Implementation Overhead of Switchable Matching Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Ettore Lorenzo Firrao, Anne-Johan Annema, Frank E. van Vliet, Bram Nauta
2017	—	`conf`	Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. A-SSCC Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta
2016	—	`conf`	Random Telegraph Signal phenomena in avalanche mode diodes: Application to SPADs. ESSDERC Vishal Agarwal, Anne-Johan Annema, Satadal Dutta, Raymond J. E. Hueting, Lis K. Nanver, Bram Nauta
2015	J	`jnl`	An Interleaved Full Nyquist High-Speed DAC Technique. IEEE J. Solid State Circuits Erik Olieman, Anne-Johan Annema, Bram Nauta
2015	J	`jnl`	On the Minimum Number of States for Switchable Matching Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Ettore Lorenzo Firrao, Anne-Johan Annema, Frank E. van Vliet, Bram Nauta
2014	—	`conf`	A 110mW, 0.04mm VLSIC Erik Olieman, Anne-Johan Annema, Bram Nauta
2013	J	`jnl`	A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance. IEEE J. Solid State Circuits Wei Cheng, Anne-Johan Annema, Gerard Wienk, Bram Nauta
2013	J	`jnl`	A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators. IEEE J. Solid State Circuits Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Gerard Wienk, Bram Nauta
2012	—	`conf`	A 0.0025mm ISSCC Anne-Johan Annema, George Goksun
2012	—	`conf`	A wideband IM3 cancellation technique for CMOS attenuators. ISSCC Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Gerard Wienk, Bram Nauta
2012	C	`conf`	Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design. DSD Benaoumeur Senouci, Anne-Johan Annema, Mark J. Bentum, Hans G. Kerkhoff
2012	J	`jnl`	RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model. IEEE Trans. Circuits Syst. I Regul. Pap. Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Jeroen A. Croon, Bram Nauta
2011	J	`jnl`	Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. Wei Cheng, Anne-Johan Annema, Jeroen A. Croon, Bram Nauta
2009	—	`conf`	A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. ESSCIRC Paul Veldhorst, George Goksun, Anne-Johan Annema, Bram Nauta, Berry A. J. Buter, Maarten Vertregt
2009	—	`conf`	A sub-1V bandgap voltage reference in 32nm FinFET technology. ISSCC Anne-Johan Annema, Paul Veldhorst, Gerben Doornbos, Bram Nauta
2008	—	`conf`	A general weak nonlinearity model for LNAs. CICC Wei Cheng, Anne-Johan Annema, Jeroen A. Croon, Dirk B. M. Klaassen, Bram Nauta
2008	C	`conf`	A multi-step P-cell for LNA design automation. ISCAS Wei Cheng, Anne-Johan Annema, Bram Nauta
2008	—	`conf`	Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology. ISSCC Mustafa Acar, Anne-Johan Annema, Bram Nauta
2007	C	`conf`	Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance. ISCAS Mustafa Acar, Anne-Johan Annema, Bram Nauta
2007	J	`jnl`	Analytical Design Equations for Class-E Power Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. Mustafa Acar, Anne-Johan Annema, Bram Nauta
2006	—	`conf`	Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers. ICECS Mustafa Acar, Anne-Johan Annema, Bram Nauta
2005	J	`jnl`	A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication. IEEE J. Solid State Circuits Sasa Radovanovic, Anne-Johan Annema, Bram Nauta
2005	—	`conf`	An audio FIR-DAC in a BCD process for high power class-D amplifiers. ESSCIRC T. S. Doorn, Ed van Tuijl, Daniël Schinkel, Anne-Johan Annema, Marco Berkhout, Bram Nauta
2005	J	`jnl`	Analog circuits in ultra-deep-submicron CMOS. IEEE J. Solid State Circuits Anne-Johan Annema, Bram Nauta, Ronald van Langevelde, Hans Tuinhout
2005	—	`conf`	Analog/RF circuit design techniques for nanometerscale IC technologies. ESSCIRC Bram Nauta, Anne-Johan Annema
2005	J	`jnl`	Bandwidth of integrated photodiodes in standard CMOS for CD/DVD applications. Microelectron. Reliab. Sasa Radovanovic, Anne-Johan Annema, Bram Nauta
2004	—	`conf`	Reducing quantization noise with recursive Sigma Delta modulators. ISCAS (1) Daniël Schinkel, Ed van Tuijl, Anne-Johan Annema
2001	J	`jnl`	5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. IEEE J. Solid State Circuits Anne-Johan Annema, Govert J. G. M. Geelen, Peter C. de Jong
2000	—	`conf`	5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technology. CICC Anne-Johan Annema, Govert Geelen, Peter C. de Jong
1999	J	`jnl`	Low-power bandgap references featuring DTMOSTs. IEEE J. Solid State Circuits Anne-Johan Annema
1995	J	`jnl`	Analog weight adaptation hardware. Neural Process. Lett. Anne-Johan Annema, Hans Wallinga
1995	—	`book`	Feed-forward neural networks - vector decomposition analysis, modelling and analog implementation. Anne-Johan Annema
1994	J	`jnl`	Learning behavior and temporary minima of two-layer neural networks. Neural Networks Anne-Johan Annema, Klaas Hoen, Hans Wallinga