Anmol Mathur

22 papers A* 5A 5B 1Misc 3Journal 6Unranked 2
YearRankTypeTitle / Venue / Authors
2022 B conf
Deep-Learning Based Beam Selection Technique for 6G Millimeter Wave Communication.
PIMRC
Satya Kumar Vankayala, Swaraj Kumar, Thirumulanathan D, Anmol Mathur, Seungil Yoon, Issaac Kommineni
2012 J jnl
Low-Power Design Using the Si2 Common Power Format.
IEEE Des. Test Comput.
Susan Carver, Anmol Mathur, Lalit Sharma, Prasad Subbarao, Steve Urish, Qi Wang
2009 J jnl
Functional Equivalence Verification Tools in High-Level Synthesis Flows.
IEEE Des. Test Comput.
Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard
2009 A* conf
Non-cycle-accurate sequential equivalence checking.
DAC
Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma
2009 Misc conf
Power Reduction Techniques and Flows at RTL and System Level.
VLSI Design
Anmol Mathur, Qi Wang
2007 A* conf
Design for Verification in System-level Models and RTL.
DAC
Anmol Mathur, Venkat Krishnaswamy
2006 Misc conf
Sequential Equivalence Checking.
VLSI Design
Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
2005 A conf
Embedded tutorial: formal equivalence checking between system-level models and RTL.
ICCAD
Alfred Kölbl, Yuan Lu, Anmol Mathur
2003 Misc conf
Graph Transformations for Improved Tree Height Reduction.
VLSI Design
G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja
2001 A* conf
Improved Merging of Datapath Operators using Information Content and Required Precision Analysis.
DAC
Anmol Mathur, Sanjeev Saluja
1998 A* conf
An Implicit Algorithm for Finding Steady States and its Application to FSM Verification.
DAC
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
1998 J jnl
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.
ACM Trans. Design Autom. Electr. Syst.
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
1998 A conf
Efficient equivalence checking of multi-phase designs using retiming.
ICCAD
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
1998 J jnl
Rate analysis for embedded systems.
ACM Trans. Design Autom. Electr. Syst.
Anmol Mathur, Ali Dasdan, Rajesh K. Gupta
1997 A* conf
An Efficient Assertion Checker for Combinational Properties.
DAC
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
1997 — conf
RATAN: A tool for rate analysis and rate constraint debugging for embedded systems.
ED&TC
Ali Dasdan, Anmol Mathur, Rajesh K. Gupta
1997 J jnl
Timing-driven placement for regular architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anmol Mathur, C. L. Liu
1996 J jnl
Generalized Kraft's Inequality and Discrete
SIAM J. Comput.
Anmol Mathur, Edward M. Reingold
1996 — conf
Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs.
ED&TC
Anmol Mathur, C. L. Liu
1995 A conf
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.
FPGA
Anmol Mathur, Kuang-Chien Chen, C. L. Liu
1995 A conf
Re-engineering of timing constrained placements for regular architectures.
ICCAD
Anmol Mathur, Kuang-Chien Chen, C. L. Liu
1994 A conf
Compression-relaxation: a new approach to performance driven placement for regular architectures.
ICCAD
Anmol Mathur, C. L. Liu