Ankit Wagle

15 papers A 2B 1C 3Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2024 J jnl
An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2023 J jnl
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula
2022 J jnl
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2022 J jnl
A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells.
CoRR
Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2022 J jnl
Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ankit Wagle, Sarma B. K. Vrudhula
2022 A conf
Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons.
ICCAD
Ayushi Dube, Ankit Wagle, Gian Singh, Sarma B. K. Vrudhula
2021 J jnl
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.
CoRR
Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2021 C conf
CIDAN: Computing in DRAM with Artificial Neurons.
ICCD
Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri
2021 J jnl
CIDAN: Computing in DRAM with Artificial Neurons.
CoRR
Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri
2020 C conf
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.
ICCD
Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2020 — conf
A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron.
ISQED
Elham Azari, Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2019 A conf
Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance.
ICCAD
Ankit Wagle, Elham Azari, Sarma B. K. Vrudhula
2019 C conf
Threshold Logic in a Flash.
ICCD
Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula
2019 J jnl
Threshold Logic in a Flash.
CoRR
Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula
2018 B conf
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area.
FPL
Ankit Wagle, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula