Anjana Dissanayake

16 papers C 1Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
MenTeR: A fully-automated Multi-agenT workflow for end-to-end RF/Analog Circuits Netlist Design.
CoRR
Pin-Han Chen, Yu-Sheng Lin, Wei-Cheng Lee, Tin-Yu Leu, Po-Hsiang Hsu, Anjana Dissanayake, Sungjin Oh, Chinq-Shiun Chiu
2024 — conf
23.2 A 1mm
ISSCC
Nicola Scolari, Franz-Xaver Pengg, Konstantinos Manetakis, Camilo A. Salazar, Alexandre Vouilloz, Ernesto Pérez Serna, Anjana Dissanayake, Pascal Persechini, Vladimir Kopta, Erwan Le Roux, Francesco Chicco, Stefano Cillo, Nicola Gerber, Cédric Barbelenet, Fabio Epifano, Paulo Augusto Dal Fabbro, Nicolas Raemy
2023 — conf
A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR.
CICC
Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers
2022 J jnl
A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver.
IEEE J. Solid State Circuits
Anjana Dissanayake, Henry L. Bishop, Steven M. Bowers, Benton H. Calhoun
2021 — conf
21.5 An Integrated 2.4GHz -91.5dBm-Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μ W at 100ms Latency.
ISSCC
Henry L. Bishop, Anjana Dissanayake, Steven M. Bowers, Benton H. Calhoun
2021 J jnl
A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring.
IEEE J. Solid State Circuits
Rishika Agarwala, Peng Wang, Henry L. Bishop, Anjana Dissanayake, Benton H. Calhoun
2021 C conf
Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design.
ISCAS
Anjana Dissanayake, Steven M. Bowers, Benton H. Calhoun
2020 — conf
A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring.
VLSI Circuits
Peng Wang, Rishika Agarwala, Henry L. Bishop, Anjana Dissanayake, Benton H. Calhoun
2020 — conf
A Multichannel, MEMS-Less -99dBm 260nW Bit-Level Duty Cycled Wakeup Receiver.
VLSI Circuits
Anjana Dissanayake, Henry L. Bishop, Jesse Moody, Henry Muhlbauer, Benton H. Calhoun, Steven M. Bowers
2020 — conf
A- 108dBm Sensitivity, -28dB SIR, 130nW to 41µW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver.
CICC
Anjana Dissanayake, Jesse Moody, Henry L. Bishop, Daniel S. Truesdell, Henry Muhlbauer, Ruochen Lu, Anming Gao, Songbin Gong, Benton H. Calhoun, Steven M. Bowers
2019 — conf
A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver.
VLSI Circuits
Jesse Moody, Anjana Dissanayake, Henry L. Bishop, Ruochen Lu, Ningxi Liu, Divya Duvvuri, Anming Gao, Daniel S. Truesdell, N. Scott Barker, Songbin Gong, Benton H. Calhoun, Steven M. Bowers
2019 J jnl
A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time.
IEEE J. Solid State Circuits
Ningxi Liu, Rishika Agarwala, Anjana Dissanayake, Daniel S. Truesdell, Sumanth Kamineni, Benton H. Calhoun
2018 — conf
A 2.4GHz, -102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver.
ASP-DAC
Oh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee
2018 — conf
A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time.
ESSCIRC
Ningxi Liu, Rishika Agarwala, Anjana Dissanayake, Daniel S. Truesdell, Sumanth Kamineni, Xing Chen, David D. Wentzloff, Benton H. Calhoun
2018 J jnl
A 45-µW, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch.
IEEE Trans. Circuits Syst. II Express Briefs
Oh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee
2017 J jnl
The Evolution of Channelization Receiver Architecture: Principles and Design Challenges.
IEEE Access
Jusung Kim, Dzuhri Radityo Utomo, Anjana Dissanayake, Seok-Kyun Han, Sang-Gug Lee