Anirudh Devgan

59 papers A* 9A 16C 2Misc 2Journal 14Unranked 16

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Powering the AI Supercycle: Design for AI and AI for Design. ISSCC Anirudh Devgan
2009	—	`conf`	Accelerated design of analog, mixed-signal circuits in Titan. ISPD Anirudh Devgan, Bülent Basaran, David Colleran, Mar Hershenson
2008	A*	`conf`	Reinventing EDA with manycore processors. DAC Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou
2007	J	`jnl`	A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan
2007	J	`jnl`	Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. J. Low Power Electron. Anand Ramalingam, Anirudh Devgan, David Z. Pan
2006	J	`jnl`	Analytical yield prediction considering leakage/performance correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester
2006	—	`conf`	Robust analytical gate delay modeling for low voltage circuits. ASP-DAC Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan
2005	—	`conf`	Achieving continuous V ASP-DAC Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan
2005	A*	`conf`	An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC Murari Mani, Anirudh Devgan, Michael Orshansky
2005	—	`conf`	Design of sub-90nm Circuits and Design Methodologies. ISQED Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi
2005	J	`jnl`	Leakage and Leakage Sensitivity Computation for Combinational Circuits. J. Low Power Electron. Emrah Acar, Anirudh Devgan, Sani R. Nassif
2005	—	`conf`	Leakage power: trends, analysis and avoidance. ASP-DAC David T. Blaauw, Anirudh Devgan, Farid N. Najm
2005	J	`jnl`	Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Des. Test Comput. Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan
2005	—	`conf`	Modeling and Design of Chip-Package Interface. ISQED Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He
2005	—	`conf`	Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown
2005	Misc	`conf`	Power Variability and Its Impact on Design. VLSI Design Anirudh Devgan, Sani R. Nassif
2005	A	`conf`	Power grid voltage integrity verification. ISLPED Maha Nizam, Farid N. Najm, Anirudh Devgan
2005	—	`conf`	Sleep transistor sizing using timing criticality and temporal currents. ASP-DAC Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan
2005	A*	`conf`	Spatially distributed 3D circuit models. DAC Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter
2005	—	`conf`	Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI Florentin Dartu, Anirudh Devgan, Noel Menezes
2004	J	`jnl`	Closed-form delay and slew metrics made easy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
2004	J	`jnl`	Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2004	A*	`conf`	Parametric yield estimation considering leakage variability. DAC Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester
2004	—	`conf`	Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. ESSCIRC Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Anirudh Devgan
2003	A	`conf`	Block-based Static Timing Analysis with Uncertainty. ICCAD Anirudh Devgan, Chandramouli V. Kashyap
2003	A	`conf`	Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. ICCAD Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan
2003	—	`conf`	Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2003	A*	`conf`	Delay and slew metrics using the lognormal distribution. DAC Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
2003	A	`conf`	Efficient techniques for gate leakage estimation. ISLPED Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
2003	A	`conf`	Full chip leakage estimation considering power supply and temperature variations. ISLPED Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif
2003	A	`conf`	Leakage and leakage sensitivity computation for combinational circuits. ISLPED Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
2002	J	`jnl`	Correction to "interconnect synthesis without wire tapering". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
2002	—	`conf`	PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
2001	J	`jnl`	Interconnect synthesis without wire tapering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
2001	—	`conf`	KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect. ASP-DAC Hao Ji, Anirudh Devgan, Wayne Wei-Ming Dai
2001	J	`jnl`	RC delay metrics for performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
2000	—	`conf`	A two moment RC delay metric for performance optimization. ISPD Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
2000	A	`conf`	An "Effective" Capacitance Based Delay Metric for RC Interconnect. ICCAD Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan
2000	A	`conf`	How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. ICCAD Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai
2000	J	`jnl`	Transient sensitivity computation in controlled explicit piecewiselinear simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston
1999	A*	`conf`	Buffer Insertion with Accurate Gate and Interconnect Delay Computation. DAC Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
1999	J	`jnl`	Buffer insertion for noise and delay optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
1999	A	`conf`	Is wire tapering worthwhile? ICCAD Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
1999	A	`conf`	Realizable reduction for RC interconnect circuits. ICCAD Anirudh Devgan, Peter R. O'Brien
1998	A*	`conf`	Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation. DAC Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov
1998	A*	`conf`	Buffer Insertion for Noise and Delay Optimization. DAC Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
1998	A	`conf`	Simulation of coupling capacitances using matrix partitioning. ICCAD Tuyen V. Nguyen, Anirudh Devgan, Ali Sadigh
1998	—	`conf`	Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). ASP-DAC Anirudh Devgan, Sandip Kundu
1997	A	`conf`	Efficient coupled noise estimation for on-chip interconnects. ICCAD Anirudh Devgan
1997	A	`conf`	State transformation in event driven explicit simulation. ICCAD Tuyen V. Nguyen, Anirudh Devgan
1997	A	`conf`	Timing analysis and optimization: from devices to systems (tutorial). ICCAD Anirudh Devgan, Leon Stok, Sandip Kundu
1997	A*	`conf`	Wire Segmenting for Improved Buffer Insertion. DAC Charles J. Alpert, Anirudh Devgan
1996	J	`jnl`	Transient simulation of integrated circuits in the charge-voltage plane. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anirudh Devgan
1995	C	`conf`	Accurate device modeling techniques for efficient timing simulation of integrated circuits. ICCD Anirudh Devgan
1995	A	`conf`	Efficient and accurate transient simulation in charge-voltage plane. ICCAD Anirudh Devgan
1995	Misc	`conf`	Efficient simulation of interconnect and mixed analog-digital circuits in ACES. VLSI Design Anirudh Devgan, Ronald A. Rohrer
1994	J	`jnl`	Adaptively controlled explicit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anirudh Devgan, Ronald A. Rohrer
1993	C	`conf`	ACES: A Transient Simulation Strategy for Integrated Circuits. ICCD Anirudh Devgan, Ronald A. Rohrer
1993	A	`conf`	Event driven adaptively controlled explicit simulation of integrated circuits. ICCAD Anirudh Devgan, Ronald A. Rohrer