Anirban Sengupta

141 papers B 1C 6Journal 82Unranked 50
YearRankTypeTitle / Venue / Authors
2026 J jnl
High-Level Synthesis-Based Forensic Watermarking of Hardware IPs Using IP Vendor's DNA Signature.
IEEE Embed. Syst. Lett.
Anirban Sengupta, Nabendu Bhui, Aditya Anshul
2026 J jnl
SHiELD: Functional Obfuscation of DSP Cores Using HLS Based One-Way Random Function and Reconfigurable Composite Switching Obfuscation Cells.
ACM Trans. Embed. Comput. Syst.
Anirban Sengupta, Aditya Anshul, Nabendu Bhui
2025 J jnl
HLS Trojan Classification and Its Detection Techniques for CAD-Based IP Designs.
IT Prof.
Anirban Sengupta, Vishal Chourasia, Nabendu Bhui
2025 J jnl
Hardware security against IP piracy using secure fingerprint encrypted fused amino-acid biometric with facial anthropometric signature.
Microprocess. Microsystems
Anirban Sengupta, Aditya Anshul, Ayush Kumar Singh
2025 — conf
Leveraging Multi-Layer Crypto-Logic Cross-Coupled with Encoded Code Converter and Conditional Control Flow for Robust Key-Based HLS IP Watermarking.
SOCC
Nabendu Bhui, Anirban Sengupta
2025 — conf
Secure Optimized Hardware IP Design using Key-driven Hash Slicing based HLS Watermarking Integrated with Krill-Herd DSE.
SOCC
Aditya Anshul, Anirban Sengupta, Vishal Chourasia
2025 J jnl
Securing Hardware IP Core for CE Systems Using Fingerprint Biometric Integrated With Microscopic Fingerprint Features and Design Encoded Hash.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Nabendu Bhui
2025 J jnl
Security Vulnerability (Backdoor Trojan) During Machine Learning Accelerator Design Phases.
IT Prof.
Anirban Sengupta, Aditya Anshul, Vishal Chourasia, Nabendu Bhui
2025 J jnl
Time-Bomb HLS Trojan for Performance Degradation Payload.
IEEE Des. Test
Anirban Sengupta, Nabendu Bhui
2025 J jnl
Watermarking of Transient Fault-Detectable IP Designs Using Multivariate HLS Scheduling Based Multimodal Security.
IET Comput. Digit. Tech.
Anirban Sengupta, Vishal Chourasia, Nabendu Bhui, Aditya Anshul
2024 J jnl
A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches.
IEEE Des. Test
Anirban Sengupta, Aditya Anshul
2024 J jnl
Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP Against Piracy.
SN Comput. Sci.
Rahul Chaurasia, Anirban Sengupta
2024 — conf
Gen-Sign: HLS Based Watermarking Using IP Vendor's Feistel Cipher Encrypted Genomic Signature for Protecting CNN and Image Processing Filter Cores Against Piracy.
iSES
Anirban Sengupta, Vishal Chourasia, Ayush Kumar Singh
2024 — conf
HLS Based Hardware Watermarking Using IP Seller's Superimposed Facial Anthropometric Features.
iSES
Anirban Sengupta, Aditya Anshul, Vishal Chourasia
2024 — conf
HLS Based Rapid Pareto Front Search of Watermarked Convolutional Layer IP Design.
iSES
Anirban Sengupta, Vishal Chourasia
2024 — conf
HLS Scheduling Driven Encoded Watermarking for Secure Convolutional Layer IP Design in CNN.
ICCE-Taiwan
Anirban Sengupta, Vishal Chourasia, Aditya Anshul
2024 — conf
HLS based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature.
SOCC
Vishal Chourasia, Anirban Sengupta, Rahul Chaurasia
2024 — conf
HLS driven Hybrid GA-PSO for Design Space Exploration of Optimal Palmprint Biometric based IP Watermark and Loop Unrolling Factor.
iSES
Anirban Sengupta, Vishal Chourasia, Nitish Kumar
2024 J jnl
Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint Signature.
SN Comput. Sci.
Anirban Sengupta, Aditya Anshul
2024 J jnl
M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs.
IEEE Embed. Syst. Lett.
Anirban Sengupta, Aditya Anshul, Vishal Chourasia, Nitish Kumar
2024 J jnl
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS.
Integr.
Rahul Chaurasia, Anirban Sengupta
2024 J jnl
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack.
IEEE Embed. Syst. Lett.
Mahendra Rathor, Anirban Sengupta
2024 — conf
Robust Watermarking of Loop Unrolled Convolution Layer IP Design for CNN using 4-variable Encoded Register Allocation.
ICCE-Taiwan
Anirban Sengupta, Vishal Chourasia, Aditya Anshul, Nitish Kumar
2024 — conf
SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan Fortification.
iSES
Anirban Sengupta, Rahul Chaurasia
2024 — conf
Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN Applications.
iSES
Rahul Chaurasia, Anirban Sengupta
2024 J jnl
Secure FFT IP Using C-Way Partitioning-Based Obfuscation and Fingerprint.
IEEE Des. Test
Anirban Sengupta, Rahul Chaurasia
2024 — conf
SecureHD: Designing Low-Cost Reliable and Security Aware Hardware Accelerators During High-Level Synthesis for Computationally Intensive Application Frameworks.
iSES
Rahul Chaurasia, Anirban Sengupta
2024 J jnl
Securing Reusable IP Cores Using Voice Biometric Based Watermark.
IEEE Trans. Dependable Secur. Comput.
Mahendra Rathor, Aditya Anshul, Anirban Sengupta
2024 J jnl
Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework.
IEEE Access
Anirban Sengupta, Aditya Anshul
2023 J jnl
Biometrics for Hardware Security and Trust: Discussion and Analysis.
IT Prof.
Anirban Sengupta, Mahendra Rathor, Rahul Chaurasia
2023 — conf
Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics.
iSES
Rahul Chaurasia, Anirban Sengupta
2023 J jnl
Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis.
Microprocess. Microsystems
Aditya Anshul, Anirban Sengupta
2023 J jnl
Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis.
Microprocess. Microsystems
Anirban Sengupta, Aditya Anshul, Rahul Chaurasia
2023 J jnl
Exploring Handwritten Signature Image Features for Hardware Security.
IEEE Trans. Dependable Secur. Comput.
Mahendra Rathor, Anirban Sengupta, Rahul Chaurasia, Aditya Anshul
2023 J jnl
Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs.
Comput. Electr. Eng.
Anirban Sengupta, Rahul Chaurasia, K. Bharath
2023 — conf
Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template.
DFT
Rahul Chaurasia, Abhinav Reddy Asireddy, Anirban Sengupta
2023 — conf
Fusing IP vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters.
ICM
Anirban Sengupta, Aditya Anshul, Sumer Thakur, Chirag Kothari
2023 — conf
Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller's Fingerprint Encrypted Amino Acid Biometric Sample.
AsianHOST
Anirban Sengupta, Rahul Chaurasia, Aditya Anshul
2023 — conf
Key-Driven Multi-Layered Structural Obfuscation of IP cores using Reconfigurable Obfuscator based Network Challenge and Switch Control Logic.
iSES
Anirban Sengupta, Aditya Anshul
2023 — conf
Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO.
iSES
Aditya Anshul, Anirban Sengupta
2023 J jnl
PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis.
Expert Syst. Appl.
Aditya Anshul, Anirban Sengupta
2023 J jnl
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.
Comput. Electr. Eng.
Mahendra Rathor, Aditya Anshul, K. Bharath, Rahul Chaurasia, Anirban Sengupta
2023 J jnl
Retinal Biometric for Securing JPEG-Codec Hardware IP Core for CE Systems.
IEEE Trans. Consumer Electron.
Rahul Chaurasia, Anirban Sengupta
2023 J jnl
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key.
IEEE Trans. Very Large Scale Integr. Syst.
Anirban Sengupta, Rahul Chaurasia, Aditya Anshul
2023 — conf
Secured and Optimized Hardware Accelerators using Key-Controlled Encoded Hash Slices and Firefly Algorithm based Exploration.
ICM
Anirban Sengupta, Aditya Anshul, Chirag Kothari, Sumer Thakur
2023 — conf
Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure.
iSES
Anirban Sengupta, Rahul Chaurasia
2022 — conf
Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems.
iSES
Aditya Anshul, K. Bharath, Anirban Sengupta
2022 — ch.
Hardware (IP) Watermarking During Behavioral Synthesis.
Behavioral Synthesis for Hardware Security
Anirban Sengupta, Mahendra Rathor
2022 — conf
IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints.
iSES
Aditya Anshul, Anirban Sengupta
2022 J jnl
Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems.
IEEE Consumer Electron. Mag.
Rahul Chaurasia, Aditya Anshul, Anirban Sengupta, Shikha Gupta
2022 J jnl
Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Rahul Chaurasia
2022 J jnl
Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression.
IEEE Access
Anirban Sengupta, Rahul Chaurasia
2022 — conf
Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core.
iSES
Rahul Chaurasia, Anirban Sengupta
2022 — conf
Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing.
iSES
Rahul Chaurasia, Anirban Sengupta
2021 J jnl
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Hu, Chip-Hong Chang, Anirban Sengupta, Swarup Bhunia, Ryan Kastner, Hai Li
2021 J jnl
Contact-Less Palmprint Biometric for Securing DSP Coprocessors Used in CE Systems.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Rahul Chaurasia, Tarun Reddy
2021 J jnl
Facial Biometric for Securing Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
Anirban Sengupta, Mahendra Rathor
2021 — conf
Securing Reusable Hardware IP cores using Palmprint Biometric.
iSES
Rahul Chaurasia, Anirban Sengupta
2021 — conf
Signature Biometric based Authentication of IP Cores for Secure Electronic Systems.
iSES
Mahendra Rathor, Anirban Sengupta
2020 J jnl
Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Mahendra Rathor
2020 J jnl
IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems.
IEEE Trans. Consumer Electron.
Mahendra Rathor, Anirban Sengupta
2020 J jnl
Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Mahendra Rathor
2020 J jnl
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting.
IEEE Trans. Very Large Scale Integr. Syst.
Anirban Sengupta, Mahendra Rathor
2020 — conf
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography.
ICCE-Berlin
Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta
2020 J jnl
Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems.
IEEE Access
Anirban Sengupta, Mahendra Rathor
2019 — conf
Crypto based Multi-Variable Fingerprinting for Protecting DSP cores.
ICCE-Berlin
Anirban Sengupta, Utkarsh Kumar Singh, Piyush Kalkute Premchand
2019 C conf
Design Pruning of DSP Kernel for Multi Objective IP Core Architecture.
ICCE
Anirban Sengupta
2019 J jnl
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019 J jnl
Embedding Digital Signature Using Encrypted-Hashing for Protection of DSP Cores in CE.
IEEE Trans. Consumer Electron.
Anirban Sengupta, E. Ranjith Kumar, N. Prajwal Chandra
2019 — conf
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic.
ICCE-Berlin
Mahendra Rathor, Anirban Sengupta
2019 — conf
Hardware Steganography for IP Core Protection of Fault Secured DSP Cores.
ICCE-Berlin
Anirban Sengupta, Gargi Gupta, Harshit Jalan
2019 J jnl
IP Core Steganography for Protecting DSP Kernels Used in CE Systems.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Mahendra Rathor
2019 C conf
Improved Delay Estimation Model for Loop based DSP cores.
ICCE
Anirban Sengupta, Mahendra Rathor
2019 — ch.
Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework.
Security and Fault Tolerance in Internet of Things
Anirban Sengupta, Dipanjan Roy
2019 J jnl
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anirban Sengupta, Deepak Kachave, Dipanjan Roy
2019 C conf
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design.
ICCE
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty
2019 J jnl
Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters].
IEEE Consumer Electron. Mag.
Dipanjan Roy, Anirban Sengupta
2019 J jnl
Protecting DSP Kernels Using Robust Hologram-Based Obfuscation.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Mahendra Rathor
2019 — conf
Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning.
ICCE-Berlin
Anirban Sengupta, N. Prajwal Chandra, E. Ranjith Kumar
2019 J jnl
Robust Logic locking for Securing Reusable DSP Cores.
IEEE Access
Mahendra Rathor, Anirban Sengupta
2019 J jnl
Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware.
IEEE Access
Anirban Sengupta, Mahendra Rathor
2019 J jnl
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters].
IEEE Consumer Electron. Mag.
Pallabi Sarkar, Dipanjan Roy, Anirban Sengupta, Mrinal Kanti Naskar
2018 J jnl
A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC.
IEEE Access
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran
2018 J jnl
Audio and Video Technologies: Recent Advances in Consumer Electronics.
IEEE Consumer Electron. Mag.
Anirban Sengupta, Niranjan Kumar Ray
2018 J jnl
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis.
Future Gener. Comput. Syst.
Anirban Sengupta, Deepak Kachave
2018 — conf
Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption.
ISVLSI
Anirban Sengupta, Saraju P. Mohanty
2018 J jnl
Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters].
IEEE Consumer Electron. Mag.
Anirban Sengupta, Dipanjan Roy
2018 J jnl
Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran
2018 J jnl
Multi-Phase Obfuscation of Fault Secured DSP Designs With Enhanced Security Feature.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Saraju P. Mohanty, Fernando Pescador, Peter Corcoran
2018 C conf
Multi-phase watermark for IP core protection.
ICCE
Anirban Sengupta, Dipanjan Roy
2018 J jnl
Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter].
IEEE Consumer Electron. Mag.
Dipanjan Roy, Anirban Sengupta
2018 — conf
Obfuscation of Fault Secured DSP Design Through Hybrid Transformation.
ISVLSI
Anirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar
2018 J jnl
Optimizing DSP Cores Using Design Transformation [Hardware Matters].
IEEE Consumer Electron. Mag.
Dipanjan Roy, Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar
2018 C conf
Reusable intellectual property core protection for both buyer and seller.
ICCE
Anirban Sengupta, Dipanjan Roy
2018 J jnl
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters].
IEEE Consumer Electron. Mag.
Deepak Kachave, Anirban Sengupta
2018 J jnl
Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath.
IEEE Trans. Aerosp. Electron. Syst.
Anirban Sengupta, Deepak Kachave
2018 J jnl
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty
2017 — conf
A Firefly Algorithm Driven Approach for High Level Synthesis.
iNIS
Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar
2017 J jnl
Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters].
IEEE Consumer Electron. Mag.
Anirban Sengupta, Dipanjan Roy
2017 J jnl
Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools.
Adv. Eng. Softw.
Anirban Sengupta, Dipanjan Roy
2017 J jnl
DSP design protection in CE through algorithmic transformation based structural obfuscation.
IEEE Trans. Consumer Electron.
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran
2017 J jnl
Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters].
IEEE Consumer Electron. Mag.
Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar
2017 J jnl
Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection: From paper marks to hardware protection.
IEEE Consumer Electron. Mag.
Saraju P. Mohanty, Anirban Sengupta, Parthasarathy Guturu, Elias Kougianos
2017 J jnl
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions.
IEEE Trans. Very Large Scale Integr. Syst.
Anirban Sengupta, Sandip Kundu
2017 J jnl
Low cost fault tolerance against k
Microelectron. Reliab.
Anirban Sengupta, Deepak Kachave
2017 J jnl
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper).
Integr.
Anirban Sengupta, Dipanjan Roy, Saumya Bhadauria
2017 J jnl
Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis.
Future Gener. Comput. Syst.
Dipanjan Roy, Anirban Sengupta
2017 J jnl
Low-cost security aware HLS methodology.
IET Comput. Digit. Tech.
Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty
2017 J jnl
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty
2016 J jnl
Cognizance on Intellectual Property: A High-Level Perspective [Hardware Matters].
IEEE Consumer Electron. Mag.
Anirban Sengupta
2016 C conf
Embedding low cost optimal watermark during high level synthesis for reusable IP core protection.
ISCAS
Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty
2016 J jnl
Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.
IEEE Access
Anirban Sengupta, Saumya Bhadauria
2016 J jnl
IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices.
IEEE Access
Anirban Sengupta, Saraju P. Mohanty, Fabrizio Lombardi, Mark Zwolinski
2016 J jnl
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors.
Microelectron. Reliab.
Deepak Kachave, Anirban Sengupta
2016 J jnl
Intellectual Property Cores: Protection designs for CE products.
IEEE Consumer Electron. Mag.
Anirban Sengupta
2015 J jnl
Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis.
Appl. Math. Comput.
Saumya Bhadauria, Anirban Sengupta
2015 J jnl
Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing.
Adv. Eng. Softw.
Anirban Sengupta, Saumya Bhadauria
2015 — conf
Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints.
VLSI-DAT
Anirban Sengupta, Saumya Bhadauria
2015 J jnl
Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis.
Expert Syst. Appl.
Anirban Sengupta, Saumya Bhadauria
2015 — conf
Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget.
CCECE
Anirban Sengupta, Reza Sedaghat
2015 — conf
GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis.
CCECE
Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar
2015 — conf
Secure Information Processing during System-Level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS Based on User Constraints.
iNIS
Anirban Sengupta, Saumya Bhadauria
2015 J jnl
Simultaneous exploration of optimal datapath and loop based high level transformation during area-delay tradeoff in architectural synthesis using swarm intelligence.
Int. J. Knowl. Based Intell. Eng. Syst.
Anirban Sengupta, Vipul Kumar Mishra
2015 J jnl
Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget.
Microelectron. Reliab.
Anirban Sengupta, Reza Sedaghat
2015 — conf
Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis.
ACM Great Lakes Symposium on VLSI
Anirban Sengupta, Saumya Bhadauria
2015 — conf
User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis.
ISQED
Anirban Sengupta, Saumya Bhadauria
2014 J jnl
Automated exploration of datapath and unrolling factor during power-performance tradeoff in architectural synthesis using multi-dimensional PSO algorithm.
Expert Syst. Appl.
Anirban Sengupta, Vipul Kumar Mishra
2014 — conf
Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm.
CCECE
Anirban Sengupta, Saumya Bhadauria
2014 — conf
Automated parallel exploration of datapath and Unrolling Factor in High Level Synthesis using hyper-dimensional particle swarm encoding.
CCECE
Anirban Sengupta, Vipul Kumar Mishra
2014 — conf
Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget.
ICIT
Anirban Sengupta, Saumya Bhadauria
2014 B conf
Exploration of Multi-objective Tradeoff during High Level Synthesis Using Bacterial Chemotaxis and Dispersal.
KES
Anirban Sengupta, Saumya Bhadauria
2014 — conf
Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis.
ISQED
Anirban Sengupta, Vipul Kumar Mishra
2014 J jnl
MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design.
Adv. Eng. Softw.
Vipul Kumar Mishra, Anirban Sengupta
2013 — conf
A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications.
ICACCI
Anirban Sengupta
2013 — conf
D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processors.
ICACCI
Anirban Sengupta, Vipul Kumar Mishra
2012 J jnl
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels.
Swarm Evol. Comput.
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2012 J jnl
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.
Microprocess. Microsystems
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2011 — conf
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis.
ACAI
Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta
2011 — conf
Integrated design space exploration based on power-performance trade-off using genetic algorithm.
ACAI
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2011 — conf
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications.
CCECE
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal
2011 — conf
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.
CCECE
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal