Anirban Sengupta

25 papers C 3Journal 11Unranked 10
YearRankTypeTitle / Venue / Authors
2021 J jnl
Automatic Generation of Route Control Chart From Validated Signal Interlocking Plan.
IEEE Trans. Intell. Transp. Syst.
Arindam Das, Manoj Kumar Gangwar, Devleena Ghosh, Chittaranjan Mandal, Anirban Sengupta, M. Mubashshir Waris
2019 — ed.
VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers
VDAT
Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma
2018 J jnl
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation.
IET Comput. Digit. Tech.
Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha
2018 — conf
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores.
iSES
Anirban Sengupta, Deepak Kachave
2017 C conf
A Quantitative Methodology for Cloud Security Risk Assessment.
CLOSER
Srijita Basu, Anirban Sengupta, Chandan Mazumdar
2017 — conf
Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis.
iNIS
Vipul Kumar Mishra, Anirban Sengupta
2017 J jnl
Hardware Security of CE Devices [Hardware Matters].
IEEE Consumer Electron. Mag.
Anirban Sengupta
2017 J jnl
Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters].
IEEE Consumer Electron. Mag.
Anirban Sengupta
2017 — conf
Mathematical Validation of HWT Based Lossless Image Compression.
iNIS
Anirban Sengupta, Dipanjan Roy
2017 — conf
Reliability and Threat Analysis of NBTI Stress on DSP Cores.
iNIS
Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha
2016 J jnl
Design Flow of a Digital IC: The role of digital IC/SOC design in CE products.
IEEE Consumer Electron. Mag.
Anirban Sengupta
2016 J jnl
Evolution of the IP Design Process in the Semiconductor/EDA Industry Hardware Matters.
IEEE Consumer Electron. Mag.
Anirban Sengupta
2016 — conf
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis.
ISVLSI
Anirban Sengupta, Deepak Kachave
2016 — conf
Protecting Ownership of Reusable IP Core Generated during High Level Synthesis.
iNIS
Deepak Kachave, Anirban Sengupta
2016 J jnl
Soft IP Core Design Resiliency Against Terrestrial Transient Faults for CE Products [Hardware Matters].
IEEE Consumer Electron. Mag.
Anirban Sengupta
2014 J jnl
A two-phase quantitative methodology for enterprise information security risk analysis.
Comput. Syst. Sci. Eng.
Jaya Bhattacharjee, Anirban Sengupta, Chandan Mazumdar, Mridul Sankar Barik
2014 — conf
PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis.
ISED
Vipul Kumar Mishra, Anirban Sengupta
2014 — conf
Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff.
ISVLSI
Anirban Sengupta, Vipul Kumar Mishra
2014 — conf
Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality Assessment.
ICIT
Anirban Sengupta, Vipul Kumar Mishra
2011 — conf
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration.
ISQED
Anirban Sengupta, Reza Sedaghat
2011 J jnl
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).
Microprocess. Microsystems
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
2011 J jnl
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems.
Microelectron. Reliab.
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
2010 C conf
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures.
ISCAS
Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta
2010 J jnl
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective.
Microelectron. Reliab.
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
2010 C conf
Rapid design space exploration for multi parametric optimization of VLSI designs.
ISCAS
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng