Anindya Sundar Dhar

86 papers A 1C 3Misc 12Journal 54Unranked 16
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Fast Algorithm for Computation of General Integer-Order Hankel Transforms.
IEEE Signal Process. Lett.
Amitava Ghosh, Anindya Sundar Dhar, Indrajit Chakrabarti
2025 J jnl
Further Results on the Zero Redundancy Sparse Arrays for DOA Estimation.
IEEE Signal Process. Lett.
Rajen Kumar Patra, Anindya Sundar Dhar
2025 J jnl
Performance evaluation for accelerated and efficient prediction of different regression models aggravated with BPSO for enhancing area efficiency through state encoding in sequential circuits.
Swarm Evol. Comput.
Kaushik Khatua, Santanu Chattopadhyay, Anindya Sundar Dhar
2024 J jnl
A Generalized Rearranged Coprime Array Configuration for Direction-of-Arrival Estimation with Increased Degrees of Freedom.
Circuits Syst. Signal Process.
Rajen Kumar Patra, Anindya Sundar Dhar
2024 Misc conf
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation.
VLSID
Ayan Palchaudhuri, Anindya Sundar Dhar
2023 J jnl
A Novel Translated Coprime Array Configuration for Moving Platform in Direction-of-Arrival Estimation.
Circuits Syst. Signal Process.
Rajen Kumar Patra, Anindya Sundar Dhar
2023 J jnl
An Improved CACIS Configuration for DOA Estimation with Enhanced Degrees of Freedom.
Circuits Syst. Signal Process.
Rajen Kumar Patra, Anindya Sundar Dhar
2023 J jnl
Optimal Coprime Array: Properties, Optimization, and k-times extension.
Circuits Syst. Signal Process.
Rajen Kumar Patra, Anindya Sundar Dhar
2023 J jnl
Unfolded Coprime Transformed Nested Arrays for Increased DOF and Negligible Mutual Coupling.
Circuits Syst. Signal Process.
Rajen Kumar Patra, Anindya Sundar Dhar
2022 J jnl
A Novel $k$-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom.
IEEE Signal Process. Lett.
Rajen Kumar Patra, Anindya Sundar Dhar
2022 J jnl
A special coprime array configuration for increased degrees of freedom.
Digit. Signal Process.
Rajen Kumar Patra, Anindya Sundar Dhar
2022 J jnl
ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design.
IEEE Trans. Emerg. Top. Comput.
Avishek Sinha Roy, Hardik Agrawal, Anindya Sundar Dhar
2022 J jnl
FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion.
J. Parallel Distributed Comput.
Ayan Palchaudhuri, Digvijay Anand, Anindya Sundar Dhar
2022 J jnl
Novel Moving Coprime Array Configurations for Real-Valued Sources.
IEEE Signal Process. Lett.
Rajen Kumar Patra, Anindya Sundar Dhar
2021 J jnl
A Novel Nested Array for Real-Valued Sources Exploiting Array Motion.
IEEE Signal Process. Lett.
Rajen Kumar Patra, Anindya Sundar Dhar
2021 J jnl
A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation.
Circuits Syst. Signal Process.
Ayan Banerjee, Anindya Sundar Dhar
2021 J jnl
Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion.
ACM Trans. Design Autom. Electr. Syst.
Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar
2021 J jnl
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support.
J. Parallel Distributed Comput.
Ayan Palchaudhuri, Anindya Sundar Dhar
2020 J jnl
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders.
IEEE Trans. Very Large Scale Integr. Syst.
Avishek Sinha Roy, Rajdeep Biswas, Anindya Sundar Dhar
2020 A conf
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion.
FPGA
Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar
2020 Misc conf
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability.
FCCM
Ayan Palchaudhuri, Anindya Sundar Dhar
2020 J jnl
SIBAM - Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications.
IEEE Trans. Circuits Syst.
Avishek Sinha Roy, Anindya Sundar Dhar
2020 J jnl
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables.
J. Electron. Test.
Ayan Palchaudhuri, Anindya Sundar Dhar
2019 J jnl
CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism.
J. Signal Process. Syst.
Kailash Chandra Ray, Anindya Sundar Dhar
2019 — conf
Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy.
iSES
Atin Mukherjee, Anindya Sundar Dhar
2019 J jnl
Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies.
J. Parallel Distributed Comput.
Ayan Palchaudhuri, Anindya Sundar Dhar
2019 Misc conf
FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation.
ACSSC
Ayan Palchaudhuri, Anindya Sundar Dhar
2019 J jnl
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations.
J. Electron. Test.
Ayan Palchaudhuri, Anindya Sundar Dhar
2019 J jnl
Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm.
IET Circuits Devices Syst.
Tanmai Kulshreshtha, Anindya Sundar Dhar
2019 J jnl
Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise.
IEEE Trans. Very Large Scale Integr. Syst.
Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar
2019 J jnl
Triple transistor based triple modular redundancy with embedded voter circuit.
Microelectron. J.
Atin Mukherjee, Anindya Sundar Dhar
2019 Misc conf
VLSI Architectures for Jacobi Symbol Computation.
VLSID
Ayan Palchaudhuri, Anindya Sundar Dhar
2018 C conf
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders.
ISCAS
Avishek Sinha Roy, Anindya Sundar Dhar
2018 J jnl
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders.
CoRR
Avishek Sinha Roy, Anindya Sundar Dhar
2018 J jnl
Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification.
IEEE Trans. Very Large Scale Integr. Syst.
Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar
2018 J jnl
An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform.
J. Signal Process. Syst.
Kailash Chandra Ray, M. V. N. V. Prasad, Anindya Sundar Dhar
2018 J jnl
CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation.
Circuits Syst. Signal Process.
Tanmai Kulshreshtha, Anindya Sundar Dhar
2018 — conf
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs.
ARC
Ayan Palchaudhuri, Anindya Sundar Dhar
2018 Misc conf
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization.
VLSID
Ayan Palchaudhuri, Anindya Sundar Dhar
2018 — conf
Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support.
IPDPS Workshops
Ayan Palchaudhuri, Anindya Sundar Dhar
2018 J jnl
Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method.
Circuits Syst. Signal Process.
Atin Mukherjee, Anindya Sundar Dhar
2017 J jnl
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics.
IEEE Trans. Very Large Scale Integr. Syst.
Sumantra Sarkar, Ayan Biswas, Anindya Sundar Dhar, Rahul M. Rao
2017 J jnl
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities.
IEEE Trans. Very Large Scale Integr. Syst.
Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar
2017 J jnl
Algorithm/Architecture Co-design of Proportionate-type LMS Adaptive Filters for Sparse System Identification.
CoRR
Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar
2017 J jnl
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations.
J. Electron. Test.
Ayan Palchaudhuri, Anindya Sundar Dhar
2017 J jnl
CORDIC-based Hann windowed sliding DFT architecture for real-time spectrum analysis with bounded error-accumulation.
IET Circuits Devices Syst.
Tanmai Kulshreshtha, Anindya Sundar Dhar
2017 J jnl
Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs.
J. Cell. Autom.
Ayan Palchaudhuri, Amrit Anand Amresh, Anindya Sundar Dhar
2017 J jnl
Fraction phase based low energy frequency calibration: analysis and design.
IET Circuits Devices Syst.
Amitava Ghosh, Anindya Sundar Dhar, Achintya Halder
2017 J jnl
High-performance VLSI architectures for M-PSK modems.
IET Circuits Devices Syst.
Chandrakanth Mamidala, Anindya Sundar Dhar
2017 — conf
Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder.
VDAT
Mamata Panigrahy, Nirmal Chandra Behera, B. Vandana, Indrajit Chakrabarti, Anindya Sundar Dhar
2017 — conf
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs.
VDAT
Ayan Palchaudhuri, Anindya Sundar Dhar
2017 Misc conf
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs.
HiPC
Ayan Palchaudhuri, Anindya Sundar Dhar
2017 J jnl
Triple transistor based fault tolerance for resource constrained applications.
Microelectron. J.
Atin Mukherjee, Anindya Sundar Dhar
2016 J jnl
A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation.
J. Real Time Image Process.
Kausik Ghosh, Anindya Sundar Dhar
2016 — conf
Approximate conditional carry adder for error tolerant applications.
VDAT
Avishek Sinha Roy, N. Prasad, Anindya Sundar Dhar
2016 J jnl
Choice of granularity for reliable circuit design using dynamic reconfiguration.
Microelectron. Reliab.
Atin Mukherjee, Anindya Sundar Dhar
2016 Misc conf
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs.
VLSID
Ayan Palchaudhuri, Anindya Sundar Dhar
2016 J jnl
Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation.
J. Real Time Image Process.
Kausik Ghosh, Anindya Sundar Dhar
2016 J jnl
High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation.
J. Circuits Syst. Comput.
Rohan Mukherjee, Vikrant Mahajan, Anindya Sundar Dhar, Indrajit Chakrabarti
2016 — conf
High performance bit-sliced pipelined comparator tree for FPGAs.
VDAT
Ayan Palchaudhuri, Anindya Sundar Dhar
2016 J jnl
Low-Delay Parallel Architecture for Fractal Image Compression.
Circuits Syst. Signal Process.
Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar
2015 J jnl
High Performance VLSI Architecture for Three-Step Search Algorithm.
Circuits Syst. Signal Process.
Rohan Mukherjee, Keyur Sheth, Anindya Sundar Dhar, Indrajit Chakrabarti, Somnath Sengupta
2015 C conf
New triple-transistor based defect-tolerant systems for reliable digital architectures.
ISCAS
Atin Mukherjee, Anindya Sundar Dhar
2015 J jnl
Real-time fault-tolerance with hot-standby topology for conditional sum adder.
Microelectron. Reliab.
Atin Mukherjee, Anindya Sundar Dhar
2014 — conf
An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS.
VDAT
Amitava Ghosh, Anindya Sundar Dhar, Achintya Halder
2014 J jnl
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis.
J. Signal Process. Syst.
Kailash Chandra Ray, Anindya Sundar Dhar
2014 — conf
VLSI design of fast fractal image encoder.
VDAT
Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar
2013 J jnl
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer.
J. Signal Process. Syst.
Ayan Banerjee, Anindya Sundar Dhar
2012 J jnl
A Variable RF Carrier Modulation Scheme for Ultralow Power Wireless Body-Area Network.
IEEE Syst. J.
Amitava Ghosh, Achintya Halder, Anindya Sundar Dhar
2012 — conf
Design of a Fault-Tolerant Conditional Sum Adder.
VDAT
Atin Mukherjee, Anindya Sundar Dhar
2012 — conf
Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture.
ISED
Atin Mukherjee, Anindya Sundar Dhar
2012 Misc conf
Random Access Analog Memory (RA2M) for Video Signal Application.
VLSI Design
Nilanjan Chattaraj, Anindya Sundar Dhar
2010 J jnl
Architectural design and FPGA implementation of radix-4 CORDIC processor.
Microprocess. Microsystems
Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee
2010 — conf
Design of DXT architecture using current switched integrator.
APCCAS
Ashis Kumar Mal, Om Prakash Hari, Rishi Todani, Anindya Sundar Dhar
2006 C conf
Sampled analog architecture for 2-D DCT.
ISCAS
C. Thakkar, Anindya Sundar Dhar
2005 J jnl
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC.
IEEE Trans. Circuits Syst. II Express Briefs
Mrityunjoy Chakraborty, Anindya Sundar Dhar, Moon Ho Lee
2005 Misc conf
Design Issues in Switched Capacitor Ladder Filters.
VLSI Design
Arindam Basu, Anindya Sundar Dhar
2005 J jnl
Novel architecture for QAM modulator-demodulator and its generalization to multicarrier modulation.
Microprocess. Microsystems
Ayan Banerjee, Anindya Sundar Dhar
2004 Misc conf
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors.
VLSI Design
Ashis Kumar Mal, Anindya Sundar Dhar
2004 — conf
Digital controlled analog architecture for DCT and DST using capacitor switching.
ISCAS (2)
Arindam Basu, Ashis Kumar Mal, Anindya Sundar Dhar
2004 — conf
Sampled analog architecture for DCT and DST.
ISCAS (2)
Ashis Kumar Mal, Arindam Basu, Anindya Sundar Dhar
2003 — conf
Analog sampled data architecture for discrete Hartley transform for prime N.
ICECS
Ashis Kumar Mal, Anindya Sundar Dhar
2001 Misc conf
CORDIC realization of the transversal adaptive filter using a trigonometric LMS algorithm.
ICASSP
Mrityunjoy Chakraborty, Anindya Sundar Dhar, Suraiya Pervin
2001 J jnl
FPGA realization of a CORDIC based FFT processor for biomedical signal processing.
Microprocess. Microsystems
Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee
2000 — conf
Systolizing the adaptive decision feedback equalizer using a symbolic state space formulation.
EUSIPCO
Mrityunjoy Chakraborty, Suraiya Pervin, Anindya Sundar Dhar
1992 Misc conf
An Array Architecture for Computing KLT Basis Vectors.
VLSI Design
Anindya Sundar Dhar