Anh-Tuan Do

52 papers C 11Journal 16Unranked 25
YearRankTypeTitle / Venue / Authors
2024 J jnl
FeCBF: A Novel Sub-Optimal Cascaded Bloom Filter Structure Based on Feature Extraction.
IEEE Access
Quang-Manh Duong, Khoa-Sang Nguyen, Hai-Duong Nguyen, Xuan-Uoc Dao, Anh-Tuan Do, Quang-Kien Trinh
2023 J jnl
A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Lu Lu, Anh-Tuan Do
2022 J jnl
A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Yi Sheng Chong, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
2021 — conf
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP.
ESSCIRC
Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do
2021 — conf
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP.
ESSDERC
Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do
2021 J jnl
A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations.
IEEE Trans. Circuits Syst. II Express Briefs
Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Anh-Tuan Do
2020 C conf
Area and Energy Efficient 2D Max-Pooling For Convolutional Neural Network Hardware Accelerator.
IECON
Bin Zhao, Yi Sheng Chong, Anh-Tuan Do
2020 J jnl
Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding.
IEEE Trans. Circuits Syst. II Express Briefs
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim
2020 — conf
NCPower: Power Modelling for NVM-based Neuromorphic Chip.
ICONS
Zhehui Wang, Huaipeng Zhang, Tao Luo, Weng-Fai Wong, Anh-Tuan Do, Paramasivam Vishnu, Wei Zhang, Rick Siow Mong Goh
2019 — conf
0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications.
A-SSCC
Fei Li, Ming Ming Wong, Aarthy Mani, Vishnu Paramasivam, Anh-Tuan Do
2019 — conf
0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique.
SoCC
Anh-Tuan Do
2019 J jnl
A Wireless Multi-Channel Peripheral Nerve Signal Acquisition System-on-Chip.
IEEE J. Solid State Circuits
Kian Ann Ng, Chao Yuan, Astrid Rusly, Anh-Tuan Do, Bin Zhao, Shih-Chiang Liu, Wendy Yen Xian Peh, Thow Xin Yuan, Kai Voges, Sanghoon Lee, Gil Gerald Lasam Gammad, Khay-Wai Leong, John S. Ho, Silvia Bossi, Gemma Taverni, Annarita Cutrone, Shih-Cheng Yen, Yong Ping Xu
2019 J jnl
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
2019 C conf
Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm.
ISCAS
Junran Pu, Vishnu P. Nambiar, Anh-Tuan Do, Wang Ling Goh
2019 — conf
Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers.
SoCC
Yun Kwan Lee, Vishnu P. Nambiar, Junran Pu, Wang Ling Goh, Anh-Tuan Do
2019 — conf
Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function.
SoCC
Ming Ming Wong, Anh-Tuan Do
2019 — conf
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing.
SoCC
Junran Pu, Vishnu P. Nambiar, Aarthy Mani, Wang Ling Goh, Anh-Tuan Do
2017 — conf
25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme.
A-SSCC
Anh-Tuan Do, Xin Liu
2016 J jnl
0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization.
IEEE J. Solid State Circuits
Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Xin Liu, Tony Tae-Hyoung Kim
2016 — conf
A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications.
A-SSCC
Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim
2016 — conf
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm
VLSI Circuits
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
2016 — conf
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm
APCCAS
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim
2015 C conf
A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation.
ISCAS
Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim
2015 C conf
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits.
ISCAS
Seyed Mohammad Ali Zeinolabedin, Anh-Tuan Do, Kiat Seng Yeo, Tony Tae-Hyoung Kim
2015 J jnl
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bo Wang, Truc Quynh Nguyen, Anh-Tuan Do, Jun Zhou, Minkyu Je, Tony Tae-Hyoung Kim
2014 — conf
0.2 V 8T SRAM with improved bitline sensing using column-based data randomization.
A-SSCC
Anh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik-Joon Chang, Tony Tae-Hyoung Kim
2014 J jnl
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance.
IEEE J. Solid State Circuits
Anh-Tuan Do, Chun Yin, Kavitha Velayudhan, Zhao Chuan Lee, Kiat Seng Yeo, Tony Tae-Hyoung Kim
2014 C conf
A hybrid NEO-based spike detection algorithm for implantable brain-IC interface applications.
ISCAS
Anh-Tuan Do, Kiat Seng Yeo
2014 — conf
Internet of Things: Trends, challenges and applications.
ISIC
Kiat Seng Yeo, Mojy Curtis Chian, Tony Chon Wee Ng, Anh-Tuan Do
2013 J jnl
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing.
IEEE Trans. Very Large Scale Integr. Syst.
Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo
2013 C conf
A current-mode stimulator circuit with two-step charge balancing background calibration.
ISCAS
Anh-Tuan Do, Yung Sern Tan, Gordon M. Xiong, Cleo Choong, Zhi-Hui Kong, Kiat Seng Yeo
2013 C conf
An improved read/write scheme for anchorless NEMS-CMOS non-volatile memory.
ISCAS
Anh-Tuan Do, Karthik G. Jayaraman, Vincent Pott, Chua Geng Li, Pushpapraj Singh, Kiat Seng Yeo, Tony Tae-Hyoung Kim
2013 — conf
Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset.
ESSDERC
Anh-Tuan Do, Karthik G. Jayaraman, Pushpapraj Singh, Chua Geng Li, Kiat Seng Yeo, Tony Tae-Hyoung Kim
2012 — conf
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications.
NEWCAS
Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Xiaodan Zou, Lei Yao, Kuang-Wei Cheng, Minkyu Je
2012 — conf
A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor.
ISOCC
Haitao Wang, Kiat Seng Yeo, Anh-Tuan Do, Yung Sern Tan, Kai Kang, Zhenghao Lu
2012 — conf
A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems.
APCCAS
Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Lei Yao, Meng Tong Tan, Minkyu Je
2012 — conf
High energy efficient ultra-low voltage SRAM design: Device, circuit, and architecture.
ISOCC
Tony T. Kim, Bo Wang, Anh-Tuan Do
2012 — conf
Low power implantable neural recording front-end.
ISOCC
Anh-Tuan Do, Yung Sern Tan, Chun Kit Lam, Minkyu Je, Kiat Seng Yeo
2012 C conf
Modeling and optimization of a combined cooling, heating and power plant system.
ACC
Vikas Chandan, Anh-Tuan Do, Baoduo Jin, Faryar Jabbari, Jack Brouwer, Ioannis Akrotirianakis, Amit Chakraborty, Andrew G. Alleyne
2012 J jnl
Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage.
IEEE Trans. Circuits Syst. II Express Briefs
Anh-Tuan Do, Truc Quynh Nguyen, Kiat Seng Yeo, Tony Tae-Hyoung Kim
2011 — conf
A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs.
ACM Great Lakes Symposium on VLSI
Anh-Tuan Do, Xiaoliang Tan, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo
2011 C conf
A low-power CAM with efficient power and delay trade-off.
ISCAS
Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo
2011 — conf
A new match line sensing technique in Content Addressable Memory.
COOL Chips
Xiaoliang Tan, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo, Zhi-Hui Kong
2011 C conf
Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor.
VLSI-SoC
Myat Thu Linn Aung, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo
2011 J jnl
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat Seng Yeo
2011 J jnl
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low
2010 C conf
A 16Kb 10T-SRAM with 4x read-power reduction.
ISCAS
Zhi-Hui Kong, Anh-Tuan Do
2010 — conf
An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving.
APCCAS
Anh-Tuan Do, Kiat Seng Yeo, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong
2010 J jnl
Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo
2010 — conf
Low IR drop and low power parallel CAM design using gated power transistor technique.
APCCAS
Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo
2008 — conf
A full current-mode sense amplifier for low-power SRAM applications.
APCCAS
Anh-Tuan Do, Jeremy Yung Shern Low, Zhi-Hui Kong, Kiat Seng Yeo, Joshua Yung Low Yung Lih
2008 J jnl
Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing.
IEEE Trans. Circuits Syst. II Express Briefs
Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo