Angxiao Yan

15 papers C 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Cycle-Slip Compensated FMCW Digital PLL With Background Back-Tracking DPD.
IEEE J. Solid State Circuits
Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Zhihua Wang, Baoyong Chi
2026 J jnl
A D-Band Distributed MIMO FMCW Radar CMOS Transceiver.
IEEE J. Solid State Circuits
Ruichen Wan, Wei Deng, Qixiu Wu, Haikun Jia, Rui Wu, Angxiao Yan, Haowen Cai, Sanming Hu, Zhihua Wang, Baoyong Chi
2025 — conf
19.9 An 11-to-16.4GHz, 3.4GHz/µs-Slope, 5.32GHz-Chirp-Bandwidth, 0.043%-RMS-Frequency-Error FMCW Digital PLL with Posterior-Segment DPD Featuring 5-Chirp-Cycle Convergence Time.
ISSCC
Angxiao Yan, Wei Deng, Haikun Jia, Yumeng Yang, Chao Tang, Shiyan Sun, Zhihua Wang, Baoyong Chi
2025 J jnl
A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z-Compliant Joint-Radar-Communication-Location Transceiver SoC.
IEEE J. Solid State Circuits
Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Lixue Kuang, Lilan Yu, Yue Liu, Xin Liang, Zhihua Wang, Baoyong Chi
2025 J jnl
A Low-Spur and Low-Jitter Fractional Output Divider With Self-Adaption Frequency Filtering Technique.
IEEE J. Solid State Circuits
Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang, Baoyong Chi
2024 — conf
A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System.
VLSI Technology and Circuits
Ruichen Wan, Wei Deng, Qixiu Wu, Haikun Jia, W. Rui, Angxiao Yan, Haowen Cai, Sanming Hu, Zhihua Wang, Baoyong Chi
2024 J jnl
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces.
IEEE J. Solid State Circuits
Pingda Guan, Ruichang Ma, Haikun Jia, Wei Deng, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Qiuyu Peng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi
2023 — conf
A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1
ISSCC
Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang, Baoyong Chi
2023 C conf
A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator.
ISCAS
Ziying Huang, Wei Deng, Haikun Jia, Bufan Zhu, Angxiao Yan, Baoyong Chi
2023 J jnl
A D-Band Joint Radar-Communication CMOS Transceiver.
IEEE J. Solid State Circuits
Wei Deng, Zipeng Chen, Haikun Jia, Pingda Guan, Taikun Ma, Angxiao Yan, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi
2023 — conf
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology.
A-SSCC
Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Zhihua Wang, Baoyong Chi
2023 — conf
A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation.
A-SSCC
Angxiao Yan, Wei Deng, Haikun Jia, Shiwei Zhang, Baoyong Chi
2023 — conf
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.
VLSI Technology and Circuits
Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi
2023 — conf
Transceiver SoC for Wireless Indoor Sensing Data-fusion.
CICC
Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Taikun Ma, Jiajie Tang, Baoyong Chi
2022 J jnl
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation.
IEEE J. Solid State Circuits
Wei Deng, Zipeng Chen, Haikun Jia, Angxiao Yan, Shiyan Sun, Guopei Chen, Zhihua Wang, Baoyong Chi