Angie Wang - RankMe

12 papers A* 1A 1Misc 1Journal 4Unranked 5

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Dimensionality of locomotor behaviors in developing C. elegans. PLoS Comput. Biol. Cera W. Hassinan, Scott C. Sterrett, Brennan Summy, Arnav Khera, Angie Wang, Jihong Bai
2019	—	`conf`	A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. CICC Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon
2019	J	`jnl`	A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic
2019	J	`jnl`	A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. IEEE J. Solid State Circuits Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Orhan Ocal, Paul Rigge, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic
2018	—	`conf`	A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic
2018	—	`conf`	A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. ESSCIRC Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic
2018	A*	`conf`	ACED: a hardware library for generating DSP systems. DAC Angie Wang, Paul Rigge, Adam M. Izraelevitz, Chick Markley, Jonathan Bachrach, Borivoje Nikolic
2017	—	`conf`	A 0.37mm A-SSCC Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolic
2017	J	`jnl`	A 65-nm CMOS Wideband TDD Front-End With Integrated T/R Switching via PA Re-Use. IEEE J. Solid State Circuits Xiao Xiao, Amanda Pratt, Bonjern Yang, Angie Wang, Ali M. Niknejad, Elad Alon, Borivoje Nikolic
2017	A	`conf`	Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations. ICCAD Adam M. Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, Jonathan Bachrach
2016	Misc	`conf`	A generator of memory-based, runtime-reconfigurable 2N3M5K FFT engines. ICASSP Angie Wang, Jonathan Bachrach, Borivoje Nikolic
2014	—	`conf`	A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers. A-SSCC Nai-Chung Kuo, Bonjern Yang, Chaoying Wu, Lingkai Kong, Angie Wang, Michael Reiha, Elad Alon, Ali M. Niknejad, Borivoje Nikolic