Angelo Garofalo

77 papers A 8C 5Misc 1Journal 47Unranked 16

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration. CoRR Max Wipfli, Gamze Islamoglu, Navaneeth Kunhi Purayil, Angelo Garofalo, Luca Benini
2026	J	`jnl`	Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection. CoRR Michael Rogenmoser, Philippe Sauter, Chen Wu, Angelo Garofalo, Luca Benini
2025	J	`jnl`	A Flexible Template for Edge Generative AI With High-Accuracy Accelerated Softmax and GELU. IEEE J. Emerg. Sel. Topics Circuits Syst. Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. CoRR Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. ACM Comput. Surv. Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke, Stefania Perri
2025	J	`jnl`	AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems. CoRR Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini
2025	J	`jnl`	AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems. IEEE Trans. Computers Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini
2025	—	`conf`	CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor. CF Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini
2025	J	`jnl`	CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor. CoRR Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini
2025	—	`conf`	FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators. CF Victor Isachi, Alessandro Nadalini, Riccardo Fiorani Gallotta, Angelo Garofalo, Francesco Conti, Davide Rossi
2025	J	`jnl`	FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators. CoRR Victor Isachi, Alessandro Nadalini, Riccardo Fiorani Gallotta, Angelo Garofalo, Francesco Conti, Davide Rossi
2025	J	`jnl`	Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs. IEEE Des. Test Angelo Garofalo, Luca Benini
2025	—	`conf`	MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products. ASAP Gamze Islamoglu, Luca Bertaccini, Arpan Suravi Prasad, Francesco Conti, Angelo Garofalo, Luca Benini
2025	J	`jnl`	MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products. CoRR Gamze Islamoglu, Luca Bertaccini, Arpan Suravi Prasad, Francesco Conti, Angelo Garofalo, Luca Benini
2025	A	`conf`	Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units. DATE Hong Pang, Carmine Cappetta, Riccardo Massa, Athanasios Vasilopoulos, Elena Ferro, Gamze Islamoglu, Angelo Garofalo, Francesco Conti, Luca Benini, Irem Boybat, Thomas Boesch
2025	A	`conf`	Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 Project. DATE Cristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Stefania Perri, Fanny Spagnolo, Pasquale Corsonello, Sebastiano Fabio Schifano, Cristian Zambelli, Angelo Garofalo, Francesco Conti, Luca Benini
2025	—	`conf`	Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications. CF (Companion) Danilo Cammarata, Matteo Perotti, Marco Bertuletti, Angelo Garofalo, Pasquale Davide Schiavone, David Atienza, Luca Benini
2025	J	`jnl`	Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications. CoRR Danilo Cammarata, Matteo Perotti, Marco Bertuletti, Angelo Garofalo, Pasquale Davide Schiavone, David Atienza, Luca Benini
2025	—	`conf`	RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine. CF (Companion) Philip Wiese, Maurus Item, Luca Bertaccini, Yvan Tortorella, Angelo Garofalo, Luca Benini
2025	J	`jnl`	RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine. CoRR Philip Wiese, Maurus Item, Luca Bertaccini, Yvan Tortorella, Angelo Garofalo, Luca Benini
2025	A	`conf`	SoftEx: A Low Power and Flexible Softmax Accelerator with Fast Approximate Exponentiation. DATE Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2025	A	`conf`	Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring. DATE Chaoqun Liang, Thomas Benz, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Davide Rossi
2025	J	`jnl`	Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring. CoRR Chaoqun Liang, Thomas Benz, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Davide Rossi
2025	J	`jnl`	Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading. ACM Trans. Embed. Comput. Syst. Maicol Ciani, Emanuele Parisi, Alberto Musa, Francesco Barchi, Andrea Bartolini, Ari Kulmala, Rafail Psiakis, Angelo Garofalo, Andrea Acquaviva, Davide Rossi
2025	C	`conf`	VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers. ARITH Run Wang, Gamze Islamoglu, Andrea Belano, Viviane Potocnik, Francesco Conti, Angelo Garofalo, Luca Benini
2025	J	`jnl`	VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers. CoRR Run Wang, Gamze Islamoglu, Andrea Belano, Viviane Potocnik, Francesco Conti, Angelo Garofalo, Luca Benini
2025	J	`jnl`	relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication. CoRR Michael Rogenmoser, Angelo Garofalo, Luca Benini
2024	J	`jnl`	A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU. CoRR Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti
2024	—	`conf`	A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems. CF (Companion) Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi
2024	J	`jnl`	A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems. CoRR Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi
2024	A	`conf`	AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. DATE Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini
2024	J	`jnl`	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. IEEE J. Solid State Circuits Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2024	J	`jnl`	Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience. CoRR Francesco Conti, Angelo Garofalo, Davide Rossi, Giuseppe Tagliavini, Luca Benini
2024	J	`jnl`	SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications. CoRR Michael Rogenmoser, Alessandro Ottaviano, Thomas Benz, Robert Balas, Matteo Perotti, Angelo Garofalo, Luca Benini
2024	J	`jnl`	Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading. CoRR Maicol Ciani, Emanuele Parisi, Alberto Musa, Francesco Barchi, Andrea Bartolini, Ari Kulmala, Rafail Psiakis, Angelo Garofalo, Andrea Acquaviva, Davide Rossi
2024	C	`conf`	vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems. ICCD Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini
2024	J	`jnl`	vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems. CoRR Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini
2023	—	`conf`	A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. ISSCC Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini
2023	—	`conf`	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. ISVLSI Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. CoRR Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
2023	J	`jnl`	AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. CoRR Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini
2023	C	`conf`	Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case. ISCAS Maicol Ciani, Stefano Bonato, Rafail Psiakis, Angelo Garofalo, Luca Valente, Suresh Sugumar, Alessandro Giusti, Davide Rossi, Daniele Palossi
2023	J	`jnl`	Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case. CoRR Maicol Ciani, Stefano Bonato, Rafail Psiakis, Angelo Garofalo, Luca Valente, Suresh Sugumar, Alessandro Giusti, Davide Rossi, Daniele Palossi
2023	J	`jnl`	DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training. CoRR Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
2023	J	`jnl`	Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. IEEE Trans. Circuits Syst. I Regul. Pap. Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
2023	C	`conf`	ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I ISCAS Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi
2023	J	`jnl`	Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays. CoRR Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi
2023	A	`conf`	End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. DATE Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2023	A	`conf`	ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers. ISLPED Gamze Islamoglu, Moritz Scherer, Gianna Paulin, Tim Fischer, Victor J. B. Jung, Angelo Garofalo, Luca Benini
2023	J	`jnl`	ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers. CoRR Gamze Islamoglu, Moritz Scherer, Gianna Paulin, Tim Fischer, Victor J. B. Jung, Angelo Garofalo, Luca Benini
2023	—	`conf`	Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. HCS Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi
2022	J	`jnl`	A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. CoRR Manuel Le Gallo, Riduan Khaddam-Aljameh, Milos Stanisavljevic, Athanasios Vasilopoulos, Benedikt Kersting, Martino Dazzi, Geethan Karunaratne, Matthias Braendli, Abhairaj Singh, Silvia M. Mueller, Julian Büchel, Xavier Timoneda Comas, Vinay Joshi, Urs Egger, Angelo Garofalo, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, Samuel Choi, Injo Ok, Timothy Philip, Victor Chan, Mary Claire Silvestre, Ishtiaq Ahsan, Nicole Saulnier, Vijay Narayanan, Pier Andrea Francese, Evangelos Eleftheriou, Abu Sebastian
2022	J	`jnl`	A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks. CoRR Angelo Garofalo, Gianmarco Ottavi, Francesco Conti, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Angelo Garofalo, Gianmarco Ottavi, Francesco Conti, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi
2022	J	`jnl`	A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics. IEEE Trans. Parallel Distributed Syst. Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
2022	—	`conf`	Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. ESSCIRC Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti
2022	J	`jnl`	Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. CoRR Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi
2022	J	`jnl`	End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. CoRR Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi
2021	—	`conf`	A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. ESSCIRC Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, Luca Benini, Davide Rossi
2021	J	`jnl`	DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. IEEE Trans. Computers Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
2021	—	`conf`	Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs. ARCS Fabio Montagna, Giuseppe Tagliavini, Davide Rossi, Angelo Garofalo, Luca Benini
2021	J	`jnl`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. IEEE Trans. Emerg. Top. Comput. Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2021	C	`conf`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes. ARITH Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	—	`conf`	A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. ISVLSI Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. CoRR Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2020	J	`jnl`	A transprecision floating-point cluster for efficient near-sensor data analytics. CoRR Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini
2020	J	`jnl`	DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. CoRR Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti
2020	J	`jnl`	Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices. CoRR Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
2020	—	`conf`	Enabling mixed-precision quantized neural networks in extreme-edge devices. CF Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi
2020	A	`conf`	XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. DATE Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini
2020	J	`jnl`	XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. CoRR Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi
2019	Misc	`conf`	DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress. CODES+ISSS Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
2019	—	`conf`	On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification. DFT Annachiara Ruospo, Riccardo Cantoro, Ernesto Sánchez, Pasquale Davide Schiavone, Angelo Garofalo, Luca Benini
2019	—	`conf`	PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters. ICECS Angelo Garofalo, Manuele Rusci, Francesco Conti, Davide Rossi, Luca Benini
2019	J	`jnl`	PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors. CoRR Angelo Garofalo, Manuele Rusci, Francesco Conti, Davide Rossi, Luca Benini