Angela Krstic - RankMe

38 papers A* 6A 10Misc 4Journal 12Unranked 6

Year	Rank	Type	Title / Venue / Authors
2004	J	`jnl`	New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Des. Test Comput. T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
2003	J	`jnl`	Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting (Tim) Cheng
2003	A	`conf`	Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
2003	Misc	`conf`	Diagnosis of Delay Defects Using Statistical Timing Models. VTS Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou
2003	A	`conf`	Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak
2003	A*	`conf`	Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
2003	—	`conf`	Experience in critical path selection for deep sub-micron delay test and timing validation. ASP-DAC Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng
2003	A	`conf`	HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. ITC Xiaoliang Bai, Sujit Dey, Angela Krstic
2003	J	`jnl`	Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
2003	—	`conf`	On Structural vs. Functional Testing for Delay Faults. ISQED Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang
2003	A	`conf`	Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
2002	J	`jnl`	Embedded Software-Based Self-Test for Programmable Core-Based Designs. IEEE Des. Test Comput. Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
2002	A*	`conf`	Embedded software-based self-testing for SoC design. DAC Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
2002	A*	`conf`	False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. DAC Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
2001	A	`conf`	Delay testing considering crosstalk-induced effects. ITC Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
2001	A*	`conf`	Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
2001	J	`jnl`	Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
2000	—	`conf`	Dynamic Timing Analysis Considering Power Supply Noise Effects. ISQED Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
2000	J	`jnl`	Estimation for maximum instantaneous current through supply lines for CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
2000	J	`jnl`	Functionally Testable Path Delay Faults on a Microprocessor. IEEE Des. Test Comput. Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
2000	Misc	`conf`	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. VTS Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
2000	A	`conf`	Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. ICCAD Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
2000	—	`conf`	Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu
2000	A	`conf`	Test program synthesis for path delay faults in microprocessor cores. ITC Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
2000	J	`jnl`	Testable Path Delay Fault Cover for Sequential Circuits. J. Inf. Sci. Eng. Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng
1999	J	`jnl`	Current Directions in Automatic Test-Pattern Generation. Computer Kwang-Ting Cheng, Angela Krstic
1999	A	`conf`	Delay testing considering power supply noise effects. ITC Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
1999	J	`jnl`	Primitive delay faults: identification, testing, and design for testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
1999	Misc	`conf`	Testing High Speed VLSI Devices Using Slower Testers. VTS Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar
1997	A	`conf`	Design for Primitive Delay Fault Testability. ITC Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
1997	A*	`conf`	Post-Layout Logic Restructuring for Performance Optimization. DAC Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
1997	J	`jnl`	Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. J. Electron. Test. Angela Krstic, Kwang-Ting Cheng
1997	A*	`conf`	Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. DAC Angela Krstic, Kwang-Ting Cheng
1996	J	`jnl`	Generation of High Quality Tests for Robustly Untestable Path Delay Faults. IEEE Trans. Computers Kwang-Ting Cheng, Angela Krstic, Hsi-Chuan Chen
1996	A	`conf`	Identification and Test Generation for Primitive Faults. ITC Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
1996	—	`conf`	Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability. ED&TC Angela Krstic, Kwang-Ting Cheng
1996	—	`conf`	Testable path delay fault cover for sequential circuits. EURO-DAC Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
1995	Misc	`conf`	Generation of high quality tests for functional sensitizable paths. VTS Angela Krstic, Kwang-Ting Cheng