Angela Arapoyanni

56 papers A 3B 1C 9Journal 14Unranked 29

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Timing Error Tolerance in Small Core Designs for SoC Applications. IEEE Trans. Computers Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
2016	—	`conf`	Timing error mitigation in microprocessor cores. ICECS Stefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas
2015	J	`jnl`	A current monitoring technique for I Integr. Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2015	A	`conf`	A method for the estimation of defect detection probability of analog/RF defect-oriented tests. DATE John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
2015	A	`conf`	Fast deployment of alternate analog test using Bayesian model fusion. DATE John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li
2015	C	`conf`	On the reuse of existing error tolerance circuitry for low power scan testing. ISCAS Anthi Anastasiou, Yiorgos Tsiatouhas, Angela Arapoyanni
2015	—	`conf`	Scan chain based at-speed diagnosis in the presence of scan output compaction schemes. Panhellenic Conference on Informatics Helen-Maria Dounavi, Yiorgos Tsiatouhas, Angela Arapoyanni
2014	J	`jnl`	The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos
2014	—	`conf`	Timing Error Tolerance in Pipeline Based Core Designs. Panhellenic Conference on Informatics Stefanos Valadimas, Angela Arapoyanni
2013	J	`jnl`	A Built-In Voltage Measurement Technique for the Calibration of RF Mixers. IEEE Trans. Instrum. Meas. John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
2013	J	`jnl`	Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. John Liaperdos, Angela Arapoyanni, Y. Tsiatouhas
2013	J	`jnl`	Effective Timing Error Tolerance in Flip-Flop Based Core Designs. J. Electron. Test. Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos
2013	C	`conf`	NBTI aging tolerance in pipeline based designs NBTI. IOLTS Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni
2012	B	`conf`	Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. ETS Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
2012	—	`conf`	Single event upset tolerance in flip-flop based microprocessor cores. DFT Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans
2012	—	`conf`	Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques. ICECS Lampros Dermentzoglou, John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
2010	C	`conf`	A Build-In Self-Test technique for RF Mixers. DDECS Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
2010	J	`jnl`	A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
2010	C	`conf`	Timing error tolerance in nanometer ICs. IOLTS Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
2008	J	`jnl`	A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
2007	—	`conf`	A Scan Flip-Flop for Low-Power Scan Operation. ICECS Yiorgos Tsiatouhas, Angela Arapoyanni, Dionisis Skias
2006	J	`jnl`	A Design Technique for Energy Reduction in NORA CMOS Logic. IEEE Trans. Circuits Syst. I Regul. Pap. Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
2006	—	`conf`	A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. ICECS Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2006	C	`conf`	High fan-in differential current mirror logic. ISCAS Y. Tsiatouhas, Angela Arapoyanni
2005	—	`conf`	A Built-In Self-Test Scheme for Differential Ring Oscillators. ISQED Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni
2005	—	`conf`	A built-in I ESSCIRC Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir
2005	—	`conf`	An embedded IDDQ testing circuit and technique. ICECS Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2005	C	`conf`	Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
2004	J	`jnl`	A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. J. Electron. Test. Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2004	J	`jnl`	A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. J. Electron. Test. Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni
2004	—	`conf`	Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . ISVLSI Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
2003	C	`conf`	A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. IOLTS Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis
2003	—	`conf`	A low power NORA circuit design technique based on charge recycling. ICECS Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis
2003	—	`conf`	A novel scheme for testing radio frequency voltage controlled oscillators. ICECS Lampros Dermentzoglou, Yiorgos Tsiatouhas, Angela Arapoyanni
2003	—	`conf`	An Embedded IDDQ Testing Architecture and Technique. ISQED Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
2003	—	`conf`	Building blocks for a 100 MS/s, 10-b, 1.8 V CMOS cascaded folding & interpolating A/D converter. ICECS Christos Kokozidis, Stamatis Bouras, Angela Arapoyanni
2002	—	`conf`	A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis
2002	J	`jnl`	A new technique for IDDQ testing in nanometer technologies. Integr. Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
2002	J	`jnl`	Charge Pump Circuits for Low-voltage Applications. VLSI Design Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni
2002	—	`conf`	Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
2002	—	`conf`	SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. ISCAS (5) A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2001	—	`conf`	A 0.35 μm SiGe BiCMOS front end for GSM low IF cellular receiver applications. ICECS Lampros Dermentzoglou, George Kamoulakos, Angela Arapoyanni
2001	—	`conf`	A CMOS differential logic for low-power and high-speed applications. ISCAS (4) Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni
2001	—	`conf`	A high-performance low-power static differential double edge-triggered flip-flop. ISCAS (4) Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou
2001	—	`conf`	A new flash memory sense amplifier in 0.18 μm CMOS technology. ICECS A. Chrisanthopoulos, Yiannis Moisiadis, A. Varagis, Y. Tsiatouhas, Angela Arapoyanni
2001	—	`conf`	New test pattern generation units for NPSF oriented memory built-in self test. ICECS A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
2000	C	`conf`	A CMOS charge pump for low voltage operation. ISCAS Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni
2000	A	`conf`	A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos
2000	C	`conf`	A high speed low power CMOS clock driver using charge recycling technique. ISCAS Ilias Bouras, Yiannis Liaperdos, Angela Arapoyanni
2000	—	`conf`	A multimode extra high IF1 image rejection receiver for TDMA applications. ICECS Lampros Dermentzoglou, Aristodimos Pneumatikakis, Angela Arapoyanni, Yiannis Moisiadis
2000	—	`conf`	A state assignment algorithm for finite state machines. ICECS Dionisis Skias, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
2000	—	`conf`	A test pattern generation unit for memory NPSF built-in self test. ICECS A. Chrisanthopoulos, George Kamoulakos, Y. Tsiatouhas, Angela Arapoyanni
2000	—	`conf`	High performance level restoration circuits for low-power reduced-swing interconnect schemes. ICECS Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni
2000	J	`jnl`	Management of charge pump circuits. Integr. George Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni
1999	—	`conf`	Novel domino logic designs. ICECS Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
1999	—	`conf`	Performance comparison of driver architectures in submicron CMOS and BiCMOS technologies for low voltage operation. ICECS Ioannis Moisiadis, Ilias Bouras, Constantin Papadas, Angela Arapoyanni