Aneesh Raveendran

12 papers Misc 5Unranked 7
YearRankTypeTitle / Venue / Authors
2026 Misc conf
BHARAT-TPM: Micro-Architecture Design of Scalable Hardware Random Number Generator for a RISC-V Trusted Platform Module.
VLSID
Soumya G. Hosmani, Raja Sekar K, Aneesh Raveendran, Vivian Desalphine, Haribabu P, S. D. Sudarsan
2024 — conf
A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications.
VDAT
Venkata Reddy Kolagatla, Aneesh Raveendran, Vivian Desalphine
2024 — conf
Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing.
VDAT
Venkata Reddy Kolagatla, Aneesh Raveendran, Vivian Desalphine
2023 Misc conf
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.
VLSID
Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut
2021 Misc conf
P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor.
VLSID
Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine
2021 Misc conf
PositGen-A Verification Suite for Posit Arithmetic.
VLSID
Annarao Kulkarni, Shashikala Gunderao Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine
2020 Misc conf
A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture.
VLSID
Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, David Selvakumar
2020 — conf
Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA.
VDAT
Vivian Desalphine, Somya Dashora, Laxita Mali, Suhas K, Aneesh Raveendran, David Selvakumar
2019 — conf
Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU.
VDAT
Aneesh Raveendran, Vinay Kumar, Vivian Desalphine, David Selvakumar
2019 — conf
RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor.
VDAT
Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, A. David Selvakumar
2015 — conf
Out of order floating point coprocessor for RISC V ISA.
VDAT
Vinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, Vivian Desalphine
2015 — conf
RISC-V out-of-order data conversion co-processor.
VDAT
Aneesh Raveendran, Vinayak Patil, Vivian Desalphine, P. M. Sobha, A. David Selvakumar