Anees Ullah

33 papers B 2C 1Journal 25Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
BEDB: a comprehensive binding energy database for molecular docking and dynamics: insights into Human Metapneumovirus (HMPV) Inhibitors.
Database J. Biol. Databases Curation
Farhan Ullah, Wajeeha Rahman, Anees Ullah, Riffat Jehan, Ali Raza, Shamsher Khan, Zarmeena, Shahid Ullah, Tianshun Gao
2024 J jnl
CO-19 PDB 2.0: A Comprehensive COVID-19 Database with Global Auto-Alerts, Statistical Analysis, and Cancer Correlations.
Database J. Biol. Databases Curation
Shahid Ullah, Yingmei Li, Wajeeha Rahman, Farhan Ullah, Muhammad Ijaz, Anees Ullah, Gulzar Ahmad, Hameed Ullah, Tianshun Gao
2024 — conf
SqueezeNIC: Low-Latency In-NIC Compression for Distributed Deep Learning.
NAIC
Achref Rebai, Mubarak Adetunji Ojewale, Anees Ullah, Marco Canini, Suhaib A. Fahmy
2023 J jnl
A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhen Gao, Jiajun Xiao, Qiang Liu, Anees Ullah, Pedro Reviriego
2023 J jnl
AVPCD: a plant-derived medicine database of antiviral phytochemicals for cancer, Covid-19, malaria and HIV.
Database J. Biol. Databases Curation
Shahid Ullah, Wajeeha Rahman, Farhan Ullah, Anees Ullah, Gulzar Ahmad, Muhammad Ijaz, Hameed Ullah, Zilong Zheng, Tianshun Gao
2023 J jnl
Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhen Gao, Yinghao Cheng, Qiang Liu, Anees Ullah, Pedro Reviriego
2023 J jnl
Error-Resilient Data Compression With Tunstall Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shanshan Liu, Pedro Reviriego, Anees Ullah, Ahmed Louri, Fabrizio Lombardi
2023 J jnl
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders.
IEEE Trans. Very Large Scale Integr. Syst.
Zhen Gao, Jinchang Shi, Qiang Liu, Anees Ullah, Pedro Reviriego
2023 J jnl
Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs.
ACM Trans. Embed. Comput. Syst.
Muhammad Awais Khan, Ali Zahir, Syed Ayaz Ali Shah, Pedro Reviriego, Anees Ullah, Nasim Ullah, Adam Khan, Hazrat Ali
2022 J jnl
Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs.
IEEE Embed. Syst. Lett.
Ali Zahir, Anees Ullah, Pedro Reviriego, Syed Riaz Ul Hassnain
2022 J jnl
Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations.
IEEE Trans. Emerg. Top. Comput.
Zhen Gao, Jinhua Zhu, Tong Yan Tyan, Anees Ullah, Pedro Reviriego
2022 J jnl
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning.
IEEE Trans. Very Large Scale Integr. Syst.
Zhen Gao, Han Zhang, Yi Yao, Jiajun Xiao, Shulin Zeng, Guangjun Ge, Yu Wang, Anees Ullah, Pedro Reviriego
2021 J jnl
Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Zhen Gao, Lingling Zhang, Yinghao Cheng, Kangkang Guo, Anees Ullah, Pedro Reviriego
2021 J jnl
Intelligent Energy-Based Modified Super Twisting Algorithm and Factional Order PID Control for Performance Improvement of PMSG Dedicated to Tidal Power System.
IEEE Access
Youcef Belkhier, Abdelyazid Achour, Nasim Ullah, Rabindra N. Shaw, Zaheer Farooq, Anees Ullah, Ali Nasser Alzaed
2021 J jnl
Switch-Based High Cardinality Node Detection.
IEEE Embed. Syst. Lett.
Anees Ullah, Pedro Reviriego, Adeel Akram, Malik Najmus Siraj
2021 J jnl
Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Uzma M. Butt, Shoab A. Khan, Anees Ullah, Abdul Khaliq, Pedro Reviriego, Ali Zahir
2020 — conf
FlexTCAM: Beyond Memory Based TCAM Emulation on FPGAs.
NFV-SDN
Anees Ullah, Salvatore Pontarelli, Pedro Reviriego
2020 J jnl
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Ali Zahir, Shadan Khan Khattak, Anees Ullah, Pedro Reviriego, Fahad Bin Muslim, Waleed Ahmad
2019 J jnl
Error Detection and Correction in SRAM Emulated TCAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Salvatore Pontarelli, Anees Ullah
2019 J jnl
PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Anees Ullah, Salvatore Pontarelli
2018 J jnl
Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs.
IEEE Trans. Computers
Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro
2018 C conf
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays.
HPSR
Pedro Reviriego, Salvatore Pontarelli, Anees Ullah, Ali Zahir, Giuseppe Bianchi
2017 J jnl
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.
J. Syst. Archit.
Luis Andrés Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer
2017 J jnl
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems.
IEEE Trans. Computers
Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
2017 J jnl
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.
Microelectron. Reliab.
Anees Ullah, Ernesto Sánchez, Luca Sterpone, Luis Andrés Cardona, Carles Ferrer
2017 J jnl
Improving the Hardware Complexity by Exploiting the Reduced Dynamics-Based Fractional Order Systems.
IEEE Access
Nasim Ullah, Anees Ullah, Asier Ibeas, Jorge A. Herrera
2015 — —
Dependable System Design for Reconfigurable Safety-Critical Applications.
Anees Ullah
2014 B conf
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs.
FPL
Ernesto Sánchez, Luca Sterpone, Anees Ullah
2014 J jnl
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs.
J. Electron. Test.
Anees Ullah, Luca Sterpone
2013 B conf
An error-detection and self-repairing method for dynamically and partially reconfigurable systems.
ETS
Matteo Sonza Reorda, Luca Sterpone, Anees Ullah
2013 — conf
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.
AHS
Luca Sterpone, Davide Sabena, Anees Ullah, Mario Porrmann, Jens Hagemeyer, Jørgen Ilstad
2013 — conf
On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs.
AHS
Luca Sterpone, Anees Ullah
2012 J jnl
Comparison Based Analysis of Different Cryptographic and Encryption Techniques Using Message Authentication Code (MAC) in Wireless Sensor Networks (WSN).
CoRR
Sadaqat ur Rehman, Muhammad Bilal, Basharat Ahmad, Khawaja Muhammad Yahya, Anees Ullah, Obaid Ur Rehman