Andy Gean Ye - RankMe

38 papers A 5B 3C 2Misc 1Journal 16Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Measuring the Minimum Power Requirement of FPGA Architectural Specifications. FPGA Andy Gean Ye, Anas Razzaq
2024	—	`conf`	A Regression-Based Approach Towards Estimating the Area, Delay and Leakage Power of Synthesizable FPGA Tiles. ICFPT Mousa Al-Qawasmi, Andy Gean Ye
2024	J	`jnl`	Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm. ACM Trans. Reconfigurable Technol. Syst. Sajjad Rostami Sani, Andy Gean Ye
2023	—	`conf`	Estimating Post-Synthesis Area, Delay, and Leakage Power of Standard Cell Based FPGA Tiles. CCECE Mousa Al-Qawasmi, Andy Gean Ye
2022	Misc	`conf`	Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm. FCCM Sajjad Rostami Sani, Anas Razzaq, Andy Gean Ye
2022	J	`jnl`	Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs. Microprocess. Microsystems Sajjad Rostami Sani, Andy Gean Ye
2022	J	`jnl`	The effect of gate voltage boosting on the power efficiency of multi-context FPGAs. Integr. Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye
2021	J	`jnl`	Designing efficient FPGA tiles for power-constrained ultra-low-power applications. Integr. Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye
2021	J	`jnl`	Static power model for CMOS and FPGA circuits. IET Comput. Digit. Tech. Anas Razzaq, Andy Gean Ye
2020	B	`conf`	Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. FPL Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye
2019	—	`conf`	A Scene-Based Augmented Reality Framework for Exhibits. ICIAR (1) Julien Li-Chee-Ming, Zheng Wu, Randy Tan, Ryan Tan, Naimul Mefraz Khan, Andy Gean Ye, Ling Guan
2018	J	`jnl`	An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures. ACM Trans. Reconfigurable Technol. Syst. Farheen Fatima Khan, Andy Gean Ye
2017	J	`jnl`	A study on the accuracy of minimum width transistor area in estimating FPGA layout area. Microprocess. Microsystems Farheen Fatima Khan, Andy Gean Ye
2017	A	`conf`	Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only). FPGA Andy Gean Ye, Karthik Ganesan
2016	J	`jnl`	Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection. Circuits Syst. Signal Process. Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye
2016	B	`conf`	An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures. FPL Farheen Fatima Khan, Andy Gean Ye
2015	C	`conf`	Minimum jitter adaptive decision feedback equalizer for 4PAM serial links. ISCAS Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye
2014	C	`conf`	A new adaptive Decision Feedback Equalizer using hexagon eye-opening monitor for multi Gbps data links. ISCAS Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye
2014	J	`jnl`	New 2-D Eye-Opening Monitor for Gb/s Serial Links. IEEE Trans. Very Large Scale Integr. Syst. Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye, Saman Sadr
2013	—	`conf`	Two-dimensional eye-opening monitor for serial links. MWSCAS Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye
2012	J	`jnl`	Analysis and architecture design of scalable fractional motion estimation for H.264 encoding. Integr. Jasmina Vasiljevic, Andy Gean Ye
2012	J	`jnl`	Effect of scaling on the area and performance of the H.264/AVC full-search fractional motion estimation algorithm on field-programmable gate arrays. IET Comput. Digit. Tech. Jasmina Vasiljevic, Andy Gean Ye
2012	J	`jnl`	Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications. Microprocess. Microsystems Shahin Sanayei Lotfabadi, Andy Gean Ye, Sridhar Krishnan
2012	J	`jnl`	Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs. Microprocess. Microsystems Omesh Mutukuda, Andy Gean Ye, Gul N. Khan
2011	—	`conf`	Audio scene analysis using parametric signal features. CCECE Hamid Asefi, Behnaz Ghoraani, Andy Gean Ye, Sridhar Krishnan
2011	—	`conf`	Hardware-software analysis of pole model features. CCECE Hamid Asefi, Behnaz Ghoraani, Andy Gean Ye, Sridhar Krishnan
2011	J	`jnl`	VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ACM Trans. Reconfigurable Technol. Syst. Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose
2010	—	`conf`	A scalability study of fractional motion estimation for H.264 encoding. CCECE Jasmina Vasiljevic, Andy Gean Ye
2010	—	`conf`	The effect of multi-bit based connections on the area efficiency of FPGAs utilizing unidirectional routing resources. FPT Omesh Mutukuda, Andy Gean Ye, Gul N. Khan
2010	J	`jnl`	Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Andy Gean Ye
2009	A	`conf`	VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. FPGA Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose
2006	J	`jnl`	Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. IEEE Trans. Very Large Scale Integr. Syst. Andy Gean Ye, Jonathan Rose
2005	B	`conf`	Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. FPL Andy Gean Ye, Jonathan Rose
2005	A	`conf`	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. FPGA Andy Gean Ye, Jonathan Rose
2004	—	`conf`	Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. FPT Andy Gean Ye, Jonathan Rose
2003	—	`conf`	Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. CICC Andy Gean Ye, Jonathan Rose, David M. Lewis
2002	—	`conf`	Synthesizing datapath circuits for FPGAs with emphasis on area minimization. FPT Andy Gean Ye, Jonathan Rose, David M. Lewis
1999	A	`conf`	Procedural Texture Mapping on FPGAs. FPGA Andy Gean Ye, David M. Lewis