Andrés Otero

60 papers A* 1A 2B 6C 2Misc 1Journal 20Unranked 28
YearRankTypeTitle / Venue / Authors
2025 — conf
A Framework for Automated CGRA Design Space Exploration with Genetic Algorithm Optimization.
DCIS
Maryam Katebzadeh, Daniel Vázquez, Andrés Otero, Alfonso Rodríguez
2025 — conf
Acceleration of C/C++ Kernels and ONNX Models on CGRAs with MLIR-Based Compilation.
DCIS
Juan Gallego, José Pedro Ferreira, Luís Alves, Daniel Vázquez, João Bispo, Alfonso Rodríguez, Nuno Paulino, Andrés Otero
2025 — conf
An FPGA-Accelerated Framework for Optimizing Decision Tree Ensembles in Supervised Learning.
IPDPS (Workshops)
Rodrigo Olmos, Andrés Otero
2025 C conf
Hardware-aware Decision Tree Ensembles for Radar Data Processing on the Edge with Online Learning.
DSD
Rodrigo Olmos, Pedro Lobo, Andrés Otero, Sergio Hernandez, Eduardo Casanueva
2025 J jnl
Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads.
ACM Trans. Reconfigurable Technol. Syst.
Juan Encinas, Alfonso Rodríguez, Andrés Otero
2025 A conf
Solving the Cold-Start Problem for the Edge: Clustering and Adaptive Deep Learning for Emotion Detection.
DATE
Junjiao Sun, Laura Gutiérrez-Martín, Celia López-Ongil, José Miranda, Jorge Portilla, Andrés Otero
2024 J jnl
A Deep Learning Approach for Fear Recognition on the Edge Based on Two-Dimensional Feature Maps.
IEEE J. Biomed. Health Informatics
Junjiao Sun, Jorge Portilla, Andrés Otero
2024 — conf
Cloud-Edge Continuum Infrastructure for Reconfigurable Multi-Accelerator Systems.
DCIS
Iñigo Díez De Ulzurrun, Juan Encinas, Alfonso Rodríguez, Andrés Otero
2024 J jnl
Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads.
Microprocess. Microsystems
Juan Encinas, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2024 — conf
Negative emotion recognition based on physiological signals using a CNN-LSTM model.
BIBM
Junjiao Sun, Jorge Portilla, Andrés Otero
2024 — conf
Open-Source Elastic CGRA Generator.
CF (Companion)
Daniel Vázquez, Alfonso Rodríguez, Andrés Otero
2024 J jnl
STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems.
CoRR
Daniel Vázquez, José Miranda, Alfonso Rodríguez, Andrés Otero, Pasquale Davide Schiavone, David Atienza
2023 A* conf
A Framework for Fast Prototyping of Photo-realistic Environments with Multiple Pedestrians.
ICRA
Sara Casao, Andrés Otero, Álvaro Serra-Gómez, Ana C. Murillo, Javier Alonso-Mora, Eduardo Montijano
2023 J jnl
A Framework for Fast Prototyping of Photo-realistic Environments with Multiple Pedestrians.
CoRR
Sara Casao, Andrés Otero, Álvaro Serra-Gómez, Ana C. Murillo, Javier Alonso-Mora, Eduardo Montijano
2023 J jnl
Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite.
CoRR
José L. Núñez-Yáñez, Andrés Otero, Eduardo de la Torre
2023 — conf
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning.
ARC
Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez
2022 — conf
A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution.
ARC
Javier Laserna, Andrés Otero, Eduardo de la Torre
2022 J jnl
Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs.
IEEE Trans. Computers
Alfonso Rodríguez, Andrés Otero, Marco Platzner, Eduardo de la Torre
2022 — conf
Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays.
DCIS
Daniel Vázquez, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2022 — conf
Just-In-Time Composition of Reconfigurable Overlays (Invited Talk).
PARMA-DITAM@HiPEAC
Rafael Zamacola, Andrés Otero, Alfonso Rodríguez, Eduardo de la Torre
2021 J jnl
A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT.
IEEE Internet Things J.
Rodrigo Marino, Cristian Wisultschew, Andrés Otero, José Manuel Lanza-Gutiérrez, Jorge Portilla, Eduardo de la Torre
2021 J jnl
Multi-grain reconfigurable and scalable overlays for hardware accelerator composition.
J. Syst. Archit.
Rafael Zamacola, Andrés Otero, Eduardo de la Torre
2021 — conf
Run-Time Monitoring and ML-Based Modeling in Reconfigurable Multi-Accelerator Systems.
DCIS
Juan Encinas, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2020 J jnl
An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems.
IEEE Access
Rafael Zamacola, Andrés Otero, Alberto García-Martínez, Eduardo de la Torre
2020 — conf
Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems.
ARC
Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2020 J jnl
Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs.
IEEE Access
Leonardo Suriano, Andrés Otero, Alfonso Rodríguez, Manuel Sánchez-Renedo, Eduardo de la Torre
2020 J jnl
Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation.
IEEE Access
Arturo Perez, Alfonso Rodríguez, Andrés Otero, David González Arjona, Álvaro Jiménez-Peralo, Miguel Ángel Verdugo, Eduardo de la Torre
2019 — conf
Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification.
DCIS
Cristian Wisultschew, Andrés Otero, Jorge Portilla, Eduardo de la Torre
2019 Misc conf
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems.
FCCM
Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre
2019 — conf
Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems.
ReCoSoC
Alberto García Ortiz, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2018 J jnl
A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images.
Remote. Sens.
Alberto García Ortiz, Alfonso Rodríguez, Raúl Guerra, Sebastián López, Andrés Otero, Roberto Sarmiento, Eduardo de la Torre
2018 J jnl
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo
Sensors
Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre
2018 — conf
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado.
ReConFig
Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre
2018 — conf
Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics.
AHS
Arturo Perez, Andrés Otero, Eduardo de la Torre
2017 — conf
Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems.
AHS
Arturo Perez, Leonardo Suriano, Andrés Otero, Eduardo de la Torre
2016 J jnl
A scalable H.264/AVC deblocking filter architecture.
J. Real Time Image Process.
Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo M. Callicó, Teresa Riesgo, Roberto Sarmiento
2015 — conf
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs.
ReCoSoC
Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2015 J jnl
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis.
IET Inf. Secur.
Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger
2014 B conf
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems.
FPL
Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2014 J jnl
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic.
Microprocess. Microsystems
Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013 — conf
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays.
IPDPS Workshops
Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo
2013 — conf
A noise-agnostic self-adaptive image processing application based on evolvable hardware.
DASIP
Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo
2013 — conf
A scalable evolvable hardware processing array.
ReConFig
Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013 B conf
A self-adaptive image processing application based on evolvable and scalable hardware.
FPL
Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo
2013 — conf
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform.
DASIP
Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013 J jnl
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing.
IEEE Trans. Computers
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2012 — conf
Automatic generation of identical routing pairs for FPGA implemented DPL logic.
ReConFig
Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2012 — conf
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems.
ReConFig
Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2012 B conf
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration.
FPL
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2012 B conf
On the automatic integration of hardware accelerators into FPGA-based embedded systems.
FPL
Christian Pilato, Andrea Cazzaniga, Gianluca Durelli, Andrés Otero, Donatella Sciuto, Marco D. Santambrogio
2012 J jnl
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks.
Sensors
Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2011 — conf
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems.
AHS
Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011 A conf
A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs.
ICME
Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo M. Callicó, Roberto Sarmiento, Teresa Riesgo
2011 — conf
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support.
AHS
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011 — conf
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems.
ReConFig
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo
2011 B conf
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs.
FPL
Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo M. Callicó, Roberto Sarmiento
2010 C conf
A Modular Peripheral to Support Self-Reconfiguration in SoCs.
DSD
Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2010 J jnl
Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors.
Int. J. Distributed Sens. Networks
Jorge Portilla, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Oliver Stecklina, Steffen Peter, Peter Langendörfer
2010 — conf
Generic Systolic Array for Run-Time Scalable Cores.
ARC
Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2010 B conf
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs.
FPL
Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva