André Sülflow

29 papers A* 1A 1B 1C 8Journal 5Unranked 12
YearRankTypeTitle / Venue / Authors
2015 — conf
Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation.
ATS
Tino Flenker, André Sülflow, Görschwin Fey
2015 J jnl
Incorporating user preferences in many-objective optimization using relation ε-preferred.
Nat. Comput.
Nicole Drechsler, André Sülflow, Rolf Drechsler
2014 J jnl
Latency Analysis for Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alexander Finder, André Sülflow, Görschwin Fey
2013 J jnl
Automated design debugging in a testbench-based verification environment.
Microprocess. Microsystems
Mehdi Dehbashi, André Sülflow, Görschwin Fey
2013 C conf
Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred.
IJCCI
Nicole Drechsler, André Sülflow, Rolf Drechsler
2012 — conf
FoREnSiC- An Automatic Debugging Environment for C Programs.
Haifa Verification Conference
Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
2011 C conf
Automated Design Debugging in a Testbench-Based Verification Environment.
DSD
Mehdi Dehbashi, André Sülflow, Görschwin Fey
2011 J jnl
Effective Robustness Analysis Using Bounded Model Checking Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
2011 B conf
Latency Analysis for Sequential Circuits.
ETS
Alexander Finder, André Sülflow, Görschwin Fey
2010 — conf
Automatic Fault Localization for Programmable Logic Controllers.
FORMS/FORMAT
André Sülflow, Rolf Drechsler
2010 J jnl
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits).
it Inf. Technol.
Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
2010 C conf
Bounded Fault Tolerance Checking.
FDL
André Sülflow
2010 C conf
RobuCheck: A Robustness Checker for Digital Circuits.
DSD
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2010 — conf
RobuCheck: a robustness checker for digital circuits.
DYADEM-FTS@EDCC
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2010 — conf
Towards Unifying Localization and Explanation for Automated Debugging.
MTV
Görschwin Fey, André Sülflow, Rolf Drechsler
2010 C conf
Using QBF to increase accuracy of SAT-based debugging.
ISCAS
André Sülflow, Görschwin Fey, Rolf Drechsler
2010 — —
WoLFram - a word level framework for formal verification and its application.
André Sülflow
2009 A* conf
Computing bounds for fault tolerance using formal techniques.
DAC
Görschwin Fey, André Sülflow, Rolf Drechsler
2009 — conf
Evaluation of Cardinality Constraints on SMT-Based Debugging.
ISMVL
André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
2009 — conf
Increasing the Accuracy of SAT-based Debugging.
MBMV
André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
2009 A conf
Increasing the accuracy of SAT-based debugging.
DATE
André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
2009 C conf
Robustness Check for Multiple Faults Using Formal Techniques.
DSD
Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2009 — conf
SWORD - Module-based SAT Solving.
Algorithms and Applications for Next Generation SAT Solvers
Robert Wille, Jean Christoph Jung, André Sülflow, Rolf Drechsler
2009 C conf
WoLFram- A Word Level Framework for Formal Verification.
IEEE International Workshop on Rapid System Prototyping
André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
2008 — conf
Debugging Design Errors by Using Unsatisfiable Cores.
MBMV
André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
2008 — conf
Using unsatisfiable cores to debug multiple design errors.
ACM Great Lakes Symposium on VLSI
André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
2007 — conf
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC.
ISMVL
André Sülflow, Rolf Drechsler
2007 C conf
Robust Multi-Objective Optimization in High Dimensional Spaces.
EMO
André Sülflow, Nicole Drechsler, Rolf Drechsler
2007 — conf
Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse.
MBMV
André Sülflow, Görschwin Fey, Rolf Drechsler