André Seznec - RankMe

135 papers A* 36A 8B 11C 7Misc 1Journal 44Unranked 26

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	PDIP: Priority Directed Instruction Prefetching. ASPLOS (2) Bhargav Reddy Godala, Sankara Prasad Ramesh, Gilles A. Pokam, Jared Stark, André Seznec, Dean M. Tullsen, David I. August
2021	—	`conf`	A Case for Partial Co-allocation Constraints in Compressed Caches. SAMOS Daniel Rodrigues Carvalho, André Seznec
2021	C	`conf`	Conciliating Speed and Efficiency on Cache Compressors. ICCD Daniel Rodrigues Carvalho, André Seznec
2021	J	`jnl`	Leveraging Value Equality Prediction for Value Speculation. ACM Trans. Archit. Code Optim. Kleovoulos Kalaitzidis, André Seznec
2021	J	`jnl`	Understanding Cache Compression. ACM Trans. Archit. Code Optim. Daniel Rodrigues Carvalho, André Seznec
2020	J	`jnl`	SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores. ACM Trans. Archit. Code Optim. Anita Tino, Caroline Collange, André Seznec
2019	C	`conf`	Compressed Cache Layout Aware Prefetching. SBAC-PAD Niloofar Charmchi, Caroline Collange, André Seznec
2019	C	`conf`	Value Speculation through Equality Prediction. ICCD Kleovoulos Kalaitzidis, André Seznec
2018	B	`conf`	Cost effective speculation with the omnipredictor. PACT Arthur Perais, André Seznec
2018	J	`jnl`	DITVA: Dynamic Inter-Thread Vectorization Architecture. J. Parallel Distributed Comput. Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy, André Seznec
2018	B	`conf`	Synergistic cache layout for reuse and compression. PACT Biswabandan Panda, André Seznec
2017	J	`jnl`	Band-Pass Prefetching: An Effective Prefetch Management Mechanism Using Prefetch-Fraction Metric in Multi-Core Systems. ACM Trans. Archit. Code Optim. Aswinkumar Sridharan, Biswabandan Panda, André Seznec
2017	B	`conf`	Compile-time function memoization. CC Arjun Suresh, Erven Rohou, André Seznec
2017	J	`jnl`	Dynamic and discrete cache insertion policies for managing shared last level caches in large multicores. J. Parallel Distributed Comput. Aswinkumar Sridharan, André Seznec
2017	J	`jnl`	On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE. ACM Trans. Archit. Code Optim. Fernando A. Endo, Arthur Perais, André Seznec
2017	J	`jnl`	Storage-Free Memory Dependency Prediction. IEEE Comput. Archit. Lett. Arthur Perais, André Seznec
2016	A*	`conf`	Cost effective physical register sharing. HPCA Arthur Perais, André Seznec
2016	A*	`conf`	Dictionary sharing: An efficient cache compression scheme for compressed caches. MICRO Biswabandan Panda, André Seznec
2016	A	`conf`	Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores. IPDPS Aswinkumar Sridharan, André Seznec
2016	C	`conf`	Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP. SBAC-PAD Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy, André Seznec
2016	J	`jnl`	EOLE: Combining Static and Dynamic Scheduling Through Value Prediction to Reduce Complexity and Increase Performance. ACM Trans. Comput. Syst. Arthur Perais, André Seznec
2016	J	`jnl`	Practical Multidimensional Branch Prediction. IEEE Micro André Seznec, Joshua San Miguel, Jorge Albericio
2016	A*	`conf`	Register sharing for equality prediction. MICRO Arthur Perais, Fernando A. Endo, André Seznec
2016	J	`jnl`	Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache. ACM Trans. Archit. Code Optim. Somayeh Sardashti, André Seznec, David A. Wood
2015	—	`conf`	An empirical high level performance model for future many-cores. Conf. Computing Frontiers Surya Narayanan, Bharath Narasimha Swamy, André Seznec
2015	J	`jnl`	BADCO: Behavioral Application-Dependent Superscalar Core Models. Int. J. Parallel Program. Ricardo A. Velásquez, Pierre Michaud, André Seznec
2015	A*	`conf`	BeBoP: A cost effective predictor infrastructure for superscalar value prediction. HPCA Arthur Perais, André Seznec
2015	A	`conf`	Branch prediction and the performance of interpreters: don't trust folklore. CGO Erven Rohou, Bharath Narasimha Swamy, André Seznec
2015	A*	`conf`	Cost-effective speculative scheduling in high performance processors. ISCA Arthur Perais, André Seznec, Pierre Michaud, Andreas Sembrant, Erik Hagersten
2015	J	`jnl`	EOLE: Toward a Practical Implementation of Value Prediction. IEEE Micro Arthur Perais, André Seznec
2015	J	`jnl`	Intercepting Functions for Memoization: A Case Study Using Transcendental Functions. ACM Trans. Archit. Code Optim. Arjun Suresh, Bharath Narasimha Swamy, Erven Rohou, André Seznec
2015	A*	`conf`	Long term parking (LTP): criticality-aware resource allocation in OOO processors. MICRO Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer, Arthur Perais, André Seznec, Pierre Michaud
2015	A*	`conf`	Prediction-based superpage-friendly TLB designs. HPCA Misel-Myrto Papadopoulou, Xin Tong, André Seznec, Andreas Moshovos
2015	J	`jnl`	Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters. ACM Trans. Archit. Code Optim. Pierre Michaud, Andrea Mondelli, André Seznec
2015	—	`conf`	Sequential and Parallel Code Sections are Different: they may require different Processors. PARMA-DITAM@HiPEAC Surya Narayanan, André Seznec
2015	A*	`conf`	The inner most loop iteration counter: a new dimension in branch history. MICRO André Seznec, Joshua San Miguel, Jorge Albericio
2014	A*	`conf`	EOLE: Paving the way for an effective implementation of value prediction. ISCA Arthur Perais, André Seznec
2014	J	`jnl`	Efficient Out-of-Order Execution of Guarded ISAs. ACM Trans. Archit. Code Optim. Nathanaël Prémillieu, André Seznec
2014	C	`conf`	Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores. SBAC-PAD Bharath Narasimha Swamy, Alain Ketterlin, André Seznec
2014	—	`conf`	Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era. SBAC-PAD (Workshops) Surya Narayanan, Bharath Narasimha Swamy, André Seznec
2014	A*	`conf`	Practical data value speculation for future high-end processors. HPCA Arthur Perais, André Seznec
2014	A*	`conf`	Skewed Compressed Caches. MICRO Somayeh Sardashti, André Seznec, David A. Wood
2013	—	`conf`	Faster unicores are still needed. ICSAMOS André Seznec
2013	B	`conf`	Message from the program chairs. PACT André Seznec, François Bodin
2013	A	`conf`	Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs. CGO Junjie Lai, André Seznec
2013	B	`ed.`	Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, Edinburgh, United Kingdom, September 7-11, 2013 PACT Christian Fensch, Michael F. P. O'Boyle, André Seznec, François Bodin
2013	B	`conf`	Selecting benchmark combinations for the evaluation of multicore throughput. ISPASS Ricardo A. Velásquez, Pierre Michaud, André Seznec
2012	—	`conf`	BADCO: Behavioral Application-Dependent Superscalar Core model. ICSAMOS Ricardo A. Velásquez, Pierre Michaud, André Seznec
2012	—	`conf`	Break down GPU execution time with an analytical method. RAPIDO Junjie Lai, André Seznec
2012	Misc	`conf`	PRETI: partitioned real-time shared cache for mixed-criticality real-time systems. RTNS Benjamin Lesage, Isabelle Puaut, André Seznec
2012	J	`jnl`	SYRANT: SYmmetric resource allocation on not-taken and taken paths. ACM Trans. Archit. Code Optim. Nathanaël Prémillieu, André Seznec
2011	A*	`conf`	A new case for the TAGE branch predictor. MICRO André Seznec
2011	—	`ch.`	Branch Predictors. Encyclopedia of Parallel Computing André Seznec
2011	—	`conf`	Decoupled zero-compressed memory. HiPEAC Julien Dusser, André Seznec
2011	J	`jnl`	Fairness Metrics for Multi-Threaded Processors. IEEE Comput. Archit. Lett. Hans Vandierendonck, André Seznec
2011	J	`jnl`	Managing SMT resource usage through speculative instruction window weighting. ACM Trans. Archit. Code Optim. Hans Vandierendonck, André Seznec
2011	A*	`conf`	Practical and secure PCM systems by online detection of malicious write streams. HPCA Moinuddin K. Qureshi, André Seznec, Luis A. Lastras, Michele Franceschini
2011	A*	`conf`	Storage free confidence estimation for the TAGE branch predictor. HPCA André Seznec
2010	A*	`ed.`	37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France ISCA André Seznec, Uri C. Weiser, Ronny Ronen
2010	J	`jnl`	A Phase Change Memory as a Secure Main Memory. IEEE Comput. Archit. Lett. André Seznec
2010	—	`conf`	Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. Conf. Computing Frontiers Pierre Michaud, Yiannakis Sazeides, André Seznec
2009	J	`jnl`	Fetch Gating Control through Speculative Instruction Window Weighting. Trans. High Perform. Embed. Archit. Compil. Hans Vandierendonck, André Seznec
2009	—	`ed.`	High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings HiPEAC André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer
2009	—	`conf`	Parallel HAVEGE. PPAM (2) Alin Suciu, Tudor Carean, André Seznec, Kinga Marton
2009	A	`conf`	Zero-content augmented caches. ICS Julien Dusser, Thomas Piquet, André Seznec
2008	J	`jnl`	Speculative return address stack management revisited. ACM Trans. Archit. Code Optim. Hans Vandierendonck, André Seznec
2007	J	`jnl`	A study of thread migration in temperature-constrained multicores. ACM Trans. Archit. Code Optim. Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou
2007	—	`conf`	Exploiting Single-Usage for Effective Memory Management. Asia-Pacific Computer Systems Architecture Conference Thomas Piquet, Olivier Rochecouste, André Seznec
2007	—	`conf`	Fetch Gating Control Through Speculative Instruction Window Weighting. HiPEAC Hans Vandierendonck, André Seznec
2007	J	`jnl`	High-Performance Embedded Architecture and Compilation Roadmap. Trans. High Perform. Embed. Archit. Compil. Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam
2007	J	`jnl`	The Idealistic GTL Predictor. J. Instr. Level Parallelism André Seznec
2007	J	`jnl`	The L-TAGE Branch Predictor. J. Instr. Level Parallelism André Seznec
2006	J	`jnl`	A case for (partially) TAgged GEometric history length branch prediction. J. Instr. Level Parallelism André Seznec, Pierre Michaud
2006	J	`jnl`	A case for a complexity-effective, width-partitioned microarchitecture. ACM Trans. Archit. Code Optim. Olivier Rochecouste, Gilles Pokam, André Seznec
2005	A*	`conf`	Analysis of the O-GEometric History Length Branch Predictor. ISCA André Seznec
2005	J	`jnl`	Conflict-Free Accesses to Strided Vectors on a Banked Cache. IEEE Trans. Computers André Seznec, Roger Espasa
2005	J	`jnl`	Genesis of the O-GEHL Branch Predictor. J. Instr. Level Parallelism André Seznec
2005	J	`jnl`	Performance implications of single thread migration on a chip multi-core. SIGARCH Comput. Archit. News Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec
2005	J	`jnl`	The strict avalanche criterion randomness test. Math. Comput. Simul. Julio César Hernández Castro, José María Sierra, André Seznec, Antonio Izquierdo, Arturo Ribagorda
2004	J	`jnl`	CASH: Revisiting Hardware Sharing in Single-Chip Parallel Processors. J. Instr. Level Parallelism Romain Dolbeau, André Seznec
2004	J	`jnl`	Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB. IEEE Trans. Computers André Seznec
2004	C	`conf`	IATO: A Flexible EPIC Simulation Environment. SBAC-PAD Amaury Darsch, André Seznec
2004	B	`conf`	On the design of state-of-the-art pseudorandom number generators by means of genetic programming. IEEE Congress on Evolutionary Computation Julio César Hernández Castro, André Seznec, Pedro Isasi
2004	A	`ed.`	Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004 ICS Paul Feautrier, James R. Goodman, André Seznec
2004	B	`conf`	Speculative software management of datapath-width for energy optimization. LCTES Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin
2004	—	`conf`	The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. ICCSA (1) Julio César Hernández Castro, José María Sierra, André Seznec
2004	—	`conf`	Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism. Euro-Par Kemal Ebcioglu, Wolfgang Karl, André Seznec, Marco Aldinucci
2003	A*	`conf`	Effective ahead Pipelining of Instruction Block Address Generation. ISCA André Seznec, Antony Fraboulet
2003	J	`jnl`	HAVEGE: A user-level software heuristic for generating empirically strong random numbers. ACM Trans. Model. Comput. Simul. André Seznec, Nicolas Sendrier
2002	A*	`conf`	Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. ISCA André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
2002	A*	`conf`	Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. MICRO André Seznec, Eric Toullec, Olivier Rochecouste
2002	A*	`conf`	Tarantula: A Vector Extension to the Alpha Architecture. ISCA Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
2001	J	`jnl`	An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. Int. J. Parallel Program. Pierre Michaud, André Seznec, Stéphan Jourdan
2001	A	`conf`	Boosting SMT Performance by Speculation Control. IPDPS Kun Luo, Manoj Franklin, Shubhendu S. Mukherjee, André Seznec
2001	A*	`conf`	Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. HPCA Pierre Michaud, André Seznec
2001	—	`conf`	Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
2000	—	`conf`	Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note). Euro-Par Thierry Lafage, André Seznec
2000	J	`jnl`	Handling Global Constraints in Compiler Strategy. Int. J. Parallel Program. Erven Rohou, François Bodin, Christine Eisenbeis, André Seznec
1999	—	`conf`	Code Cloning Tracing: A "Pay per Trace" Approach. Euro-Par Thierry Lafage, André Seznec, Erven Rohou, François Bodin
1999	—	`conf`	Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. IEEE PACT Pierre Michaud, André Seznec, Stéphan Jourdan
1999	—	`conf`	OCEANS - Optimising Compilers for Embedded Applications. Euro-Par Michel Barreteau, François Bodin, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Toru Kisuki, Peter M. W. Knijnenburg, Paul van der Mark, Andy Nisbet, Michael F. P. O'Boyle, Erven Rohou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff
1999	A*	`conf`	Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading. HPCA Sébastien Hily, André Seznec
1998	—	`conf`	Improving Cache Behavior of Dynamically Allocated Data Structures. IEEE PACT D. N. Truong, François Bodin, André Seznec
1998	—	`conf`	OCEANS: Optimising Compilers for Embedded Applications. Euro-Par Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, André Seznec, Elena Stöhr, Menno Treffers, Harry A. G. Wijshoff
1997	J	`jnl`	Decoupled Sectored Caches. IEEE Trans. Computers André Seznec
1997	—	`conf`	OCEANS: Optimizing Compilers for Embedded Applications. Euro-Par Bas Aarts, Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, Henk Schepers, André Seznec, Elena Stöhr, Marco Verhoeven, Harry A. G. Wijshoff
1997	J	`jnl`	Skewed Associativity Improves Program Performance and Enhances Predictability. IEEE Trans. Computers François Bodin, André Seznec
1997	A*	`conf`	Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. ISCA Pierre Michaud, André Seznec, Richard Uhlig
1996	—	`conf`	Branch prediction and simultaneous multithreading. IEEE PACT Sébastien Hily, André Seznec
1996	A*	`conf`	Don't Use the Page Number, But a Pointer To It. ISCA André Seznec
1996	A*	`conf`	Multiple-Block Ahead Branch Predictors. ASPLOS André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud
1995	J	`jnl`	About Cache Associativity in Low-Cost Shared Memory Multi-Microprocessors. Parallel Process. Lett. Nathalie Drach, Alain Gefflaut, Philippe Joubert, André Seznec
1995	A*	`conf`	DASC Cache. HPCA André Seznec
1995	B	`conf`	Direct-mapped versus set-associative pipelined caches. PACT Nathalie Drach, André Seznec, Daniel Windheiser
1995	J	`jnl`	Odd Memory Systems: A New Approach. J. Parallel Distributed Comput. André Seznec, Jacques Lenfant
1995	A*	`conf`	Skewed Associativity Enhances Performance Predictability. ISCA François Bodin, André Seznec
1994	A*	`conf`	Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio. ISCA André Seznec
1994	J	`jnl`	Interleaved Parallel Schemes. IEEE Trans. Parallel Distributed Syst. André Seznec, Jacques Lenfant
1993	A*	`conf`	A Case for Two-Way Skewed-Associative Caches. ISCA André Seznec
1993	C	`conf`	About Set and Skewed Associativity on Second-Level Caches. ICCD André Seznec
1993	A*	`conf`	MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines. MICRO Nathalie Drach, André Seznec
1993	A*	`conf`	Odd Memory Systems May be Quite Interesting. ISCA André Seznec, Jacques Lenfant
1993	—	`conf`	Semi-Unified Caches. ICPP (1) Nathalie Drach, André Seznec
1993	—	`conf`	Skewed-associative Caches. PARLE André Seznec, François Bodin
1992	A*	`conf`	Controlling and sequencing a heavily pipelined floating-point operator. MICRO André Seznec, Karl Courtel
1992	A*	`conf`	Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers. ISCA André Seznec, Jacques Lenfant
1992	A*	`conf`	OPAC: A floating-point coprocessor dedicated to compute-bound kernels. ISCA André Seznec, Karl Courtel
1989	A	`conf`	A asynchronous buffering network for tightly coupled multiprocessors. ICS Yvon Jégou, André Seznec
1988	A*	`conf`	Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor. ISCA André Seznec, Yvon Jégou
1988	A	`conf`	Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache. ICS André Seznec, Yvon Jégou
1987	J	`jnl`	A New Interconnection Network for SIMD Computers: The Sigma Network. IEEE Trans. Computers André Seznec
1987	B	`conf`	Optimizing Memory Throughput In a Tightly Coupled Multiprocessor. ICPP André Seznec, Yvon Jégou
1986	A*	`conf`	An Efficient Routing Control Unit for the SIGMA Network E(4). ISCA André Seznec
1986	B	`conf`	Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments. ICPP Yvon Jégou, André Seznec
1986	J	`jnl`	Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments. J. Parallel Distributed Comput. Yvon Jégou, André Seznec