André Ivanov

160 papers A 14B 1C 9Misc 15Journal 69Unranked 50
YearRankTypeTitle / Venue / Authors
2026 J jnl
Computational Bayesian Experimental Design and Inference for Assisted Linear Circuit Prototype Debug.
IEEE Access
Ian Hill, Frank Wood, André Ivanov
2025 Misc conf
Gate Leakage Current Integration-Based Dielectric Breakdown Monitor in a 12nm FinFET Process.
VTS
Mateo Rendón, Ian Hill, André Ivanov
2025 — conf
Multilevel Variability and Epistemic Uncertainty Analysis of Reliability Physics Models Through Hierarchical Probabilistic Modelling.
IRPS
Ian Hill, André Ivanov
2024 — conf
A Novel Induced Offset Voltage Sensor for Separable Wear-Out Mechanism Characterization in a 12nm FinFET Process.
IRPS
Ian Hill, Mateo Rendón, André Ivanov
2024 Misc conf
Enhanced Wear-Out Sensor Design in a 12nm Process for Separable Stress Regime Monitoring.
VTS
Ian Hill, Mateo Rendón, André Ivanov
2024 J jnl
SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation.
CoRR
Seyed Arash Sheikholeslam, André Ivanov
2024 J jnl
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network.
IEEE Des. Test
Yuxuan Pan, Zhonghua Zhou, S. Arash Sheikholeslam, André Ivanov
2023 Misc conf
Gerabaldi: A Temporal Simulator for Probabilistic IC Degradation and Failure Processes.
VTS
Ian Hill, André Ivanov
2023 J jnl
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing.
ACM Trans. Design Autom. Electr. Syst.
Zhonghua Zhou, Yuxuan Pan, Guy G. F. Lemieux, André Ivanov
2022 B conf
Prediction of Thermally Accelerated Aging Process at 28nm.
ETS
Parvez Anwar Chanawala, Ian Hill, S. Arash Sheikholeslam, André Ivanov
2022 — conf
Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural Network.
ISQED
Yuxuan Pan, Zhonghua Zhou, André Ivanov
2021 C conf
Are you for Real? Authentication in Dynamic IoT Systems.
PRDC
Mehdi Karimibiuki, Karthik Pattabiraman, André Ivanov
2019 — conf
Supervised-Learning Congestion Predictor For Routability-Driven Global Routing.
VLSI-DAT
Zhonghua Zhou, Sunmeet Chahal, Tsung-Yi Ho, André Ivanov
2018 — conf
CORGIDS: A Correlation-based Generic Intrusion Detection System.
CPS-SPC@CCS
Ekta Aggarwal, Mehdi Karimibiuki, Karthik Pattabiraman, André Ivanov
2018 C conf
DynPolAC: Dynamic Policy-Based Access Control for IoT Systems.
PRDC
Mehdi Karimibiuki, Ekta Aggarwal, Karthik Pattabiraman, André Ivanov
2018 — conf
MiniCloud: a mini storage and query service for local heterogeneous IoT devices.
IOT
Mehdi Karimibiuki, André Ivanov
2016 C conf
An improved test power optimization method by insertion of linear functions.
ISCAS
Lucheng He, Aijiao Cui, Mengyang Li, André Ivanov
2016 — conf
Local congestion and blockage aware routability analysis using adaptive flexible modeling.
ICECS
André Ivanov, Peter Hallschmid, Zhonghua Zhou
2015 J jnl
A Look at Asynchronous Design and Photonic Network-on-a-Chip (PNoC).
IEEE Des. Test
André Ivanov
2015 J jnl
A Look at Trojan Attack, Pruning, and Dependability.
IEEE Des. Test
André Ivanov
2015 C conf
A new decompressor with ordered parallel scan design for reduction of test data and test time.
ISCAS
Tingting Yu, Aijiao Cui, Mengyang Li, André Ivanov
2015 J jnl
Advances in 3-D Integrated Circuits, Systems, and CAD Tools.
IEEE Des. Test
André Ivanov
2015 J jnl
Cyber-Physplical Systems for Medical Apications.
IEEE Des. Test
André Ivanov
2015 J jnl
Microfluidics: Design and Test Solutions for Enabling Biochemistry on a Chip.
IEEE Des. Test
André Ivanov
2015 — ed.
Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015
NOCS
André Ivanov, Diana Marculescu, Partha Pratim Pande, José Flich, Karthik Pattabiraman
2015 A conf
Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection.
ICCAD
Ricardo Ochoa Gallardo, Alan J. Hu, André Ivanov, Maryam S. Mirian
2015 J jnl
Speeding Up Analog Integration and Test for Mixed-Signal SoCs.
IEEE Des. Test
André Ivanov
2014 — conf
A low-power DC-to-27-GHz transimpedance amplifier in 0.13-µm CMOS using inductive-peaking and current-reuse techniques.
MWSCAS
Amir Hossein Masnadi Shirazi, Reza Molavi, Peter Sangpil Woo, Ge Yu, Shahriar Mirabbasi, Sudip Shekhar, André Ivanov
2014 — conf
A novel tri-state device implemented with a metal gated QCA.
LASCAS
S. Arash Sheikholeslam, Cristian Grecu, André Ivanov
2014 J jnl
Design and Testing of Millimeter-Wave/Subterahertz Circuits and Systems.
IEEE Des. Test
André Ivanov
2014 — conf
Performance comparison of two wide-tuning-range 13-GHz CMOS LC-VCOs.
ICECS
Ge Yu, Shahriar Mirabbasi, André Ivanov
2014 J jnl
Revisiting DAC's 50th Anniversary.
IEEE Des. Test
André Ivanov
2014 — conf
T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges.
SoCC
Partha Pratim Pande, Alireza Nojeh, André Ivanov
2014 — conf
T2B: Carbon nanotubes and opportunities for wireless on-chip interconnect.
SoCC
Alireza Nojeh, Partha Pratim Pande, André Ivanov
2014 J jnl
The Internet of Things.
IEEE Des. Test
André Ivanov
2013 J jnl
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs.
IEEE Trans. Computers
Kyle Balston, Mehdi Karimibiuki, Alan J. Hu, André Ivanov, Steven J. E. Wilton
2012 — conf
Lazy suspect-set computation: fault diagnosis for deep electrical bugs.
ACM Great Lakes Symposium on VLSI
Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov
2012 J jnl
Multi-objective voltage island floorplanning using sequence pair representation.
Sustain. Comput. Informatics Syst.
Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov
2011 — conf
Performance and functional test of flip-flops using ring oscillator structure.
IDT
Renato P. Ribas, André Inácio Reis, André Ivanov
2011 — conf
Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC.
HLDVT
Mehdi Karimibiuki, Kyle Balston, Alan J. Hu, André Ivanov
2011 — conf
Ring oscillators for functional and delay test of latches and flip-flops.
SBCCI
Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov
2011 C conf
Self-checking test circuits for latches and flip-flops.
IOLTS
Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov
2011 — conf
Sequence pair based voltage island floorplanning.
IGCC
Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh
2010 — ed.
5th International Design and Test Workshop, IDT 2010, Abu Dhabi, UAE, 14-15 December 2010
IDT
Yervant Zorian, Imtinan Elahi, André Ivanov, Ashraf Salem
2010 J jnl
Wireless Interconnect and the Potential for Carbon Nanotubes.
IEEE Des. Test Comput.
Alireza Nojeh, André Ivanov
2009 J jnl
Application modelling and hardware description for network-on-chip benchmarking.
IET Comput. Digit. Tech.
Erno Salminen, Cristian Grecu, Timo D. Hämäläinen, André Ivanov
2009 J jnl
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.
J. Electron. Test.
Faizal Karim, Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Konrad Walus, André Ivanov, Fabrizio Lombardi
2008 J jnl
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.
IEEE Trans. Educ.
Rod Blaine Foist, Cristian Grecu, André Ivanov, Robin Turner
2008 C conf
Novel interconnect infrastructures for massive multicore chips - an overview.
ISCAS
Partha Pratim Pande, Amlan Ganguly, Benjamin Belzer, Alireza Nojeh, André Ivanov
2007 — conf
A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS.
CICC
Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov
2007 J jnl
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs
CoRR
Baosheng Wang, Yuejian Wu, André Ivanov
2007 — conf
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.
MSE
Rod Blaine Foist, André Ivanov, Robin Turner
2007 J jnl
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip.
Integr.
Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve A. Saleh, André Ivanov
2007 J jnl
Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients.
IEEE Trans. Circuits Syst. I Regul. Pap.
A. K. M. K. Mollah, Roberto Rosales, Sassan Tabatabaei, James Cicalo, André Ivanov
2007 C conf
Essential Fault-Tolerance Metrics for NoC Infrastructures.
IOLTS
Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh
2007 — conf
On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.
DFT
Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Faizal Karim, Konrad Walus, André Ivanov
2007 J jnl
Test scheduling for built-in self-tested embedded SRAMs with data retention faults.
IET Comput. Digit. Tech.
Qiang Xu, Baosheng Wang, André Ivanov, Fung Yu Young
2007 J jnl
Testing Network-on-Chip Communication Fabrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande
2007 — conf
Towards Open Network-on-Chip Benchmarks.
NOCS
Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu
2006 Misc conf
BIST for Network-on-Chip Interconnect Infrastructures.
VTS
Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
2006 J jnl
Fast detection of data retention faults and other SRAM cell open defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov
2006 — conf
Low Power SoC Memory BIST.
DFT
Yuejian Wu, André Ivanov
2006 — conf
NoC Interconnect Yield Improvement Using Crosspoint Redundancy.
DFT
Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande
2006 C conf
On-line Fault Detection and Location for NoC Interconnects.
IOLTS
Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande
2006 Misc conf
Session Abstract.
VTS
André Ivanov
2006 J jnl
System-on-Chip: Reuse and Integration.
Proc. IEEE
Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov
2005 — conf
A 0.35µm CMOS comparator circuit for high-speed ADC applications.
ISCAS (6)
Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov
2005 — conf
A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS.
ISCAS (6)
Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov
2005 A conf
A DDJ calibration methodology for high-speed test and measurement equipments.
ITC
Touraj Farahmand, Sassan Tabatabaei, Freddy Ben-Zeev, André Ivanov
2005 A conf
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs.
DATE
Baosheng Wang, Yuejian Wu, André Ivanov
2005 J jnl
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.
J. Electron. Test.
Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei
2005 — conf
A retention-aware test power model for embedded SRAM.
ASP-DAC
Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov
2005 J jnl
An Analog Circuit Fault Characterization Methodology.
J. Electron. Test.
Yvan Maidon, Thomas Zimmer, André Ivanov
2005 J jnl
Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects.
IEEE Trans. Instrum. Meas.
Andy Kuo, Roberto Rosales, Touraj Farahmand, Sassan Tabatabaei, André Ivanov
2005 J jnl
Design, Synthesis, and Test of Networks on Chips.
IEEE Des. Test Comput.
Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli
2005 — conf
Effect of traffic localization on energy dissipation in NoC-based interconnect.
ISCAS (2)
Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh
2005 J jnl
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.
IEEE Des. Test Comput.
André Ivanov, Giovanni De Micheli
2005 — conf
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.
DFT
Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh
2005 J jnl
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.
IEEE Trans. Computers
Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh
2005 Misc conf
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.
VTS
Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian
2005 J jnl
Timing analysis of network on chip architectures for MP-SoC platforms.
Microelectron. J.
Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
2004 — conf
A Scalable Communication-Centric SoC Interconnect Architecture.
ISQED
Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
2004 — conf
Designs for Reducing Test Time of Distributed Small Embedded SRAMs.
DFT
Baosheng Wang, Yuejian Wu, André Ivanov
2004 J jnl
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates.
IEEE Des. Test Comput.
André Ivanov, Fabrizio Lombardi, Cecilia Metra
2004 J jnl
Indirect test architecture for SoC testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohsen Nahvi, André Ivanov
2004 A conf
Jitter Models and Measurement Methods for High-Speed Serial Interconnects.
ITC
Andy Kuo, Touraj Farahmand, Nelson Ou, André Ivanov, Sassan Tabatabaei
2004 J jnl
Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects.
IEEE Des. Test Comput.
Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, André Ivanov
2004 Misc conf
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode.
VLSI Design
Josh Yang, Baosheng Wang, André Ivanov
2004 Misc conf
Reducing Embedded SRAM Test Time under Redundancy Constraints.
VTS
Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian
2004 Misc conf
Sensing temperature in CMOS circuits for Thermal Testing.
VTS
Josep Altet, Antonio Rubio, M. Amine Salhi, Jose Luis Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov
2004 — conf
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.
ACM Great Lakes Symposium on VLSI
Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
2003 J jnl
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.
IEEE Des. Test Comput.
Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei
2003 Misc conf
An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores.
VTS
Mohsen Nahvi, André Ivanov
2003 — conf
Analog IP design flow for SoC applications.
ISCAS (4)
Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov
2003 — conf
Design of a switch for network on chip applications.
ISCAS (5)
Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh
2003 J jnl
Guest Editorial.
J. Electron. Test.
André Ivanov
2003 — conf
High-Throughput Switch-Based Interconnect for Future SoCs.
IWSOC
Partha Pratim Pande, Cristian Grecu, André Ivanov
2003 — conf
Reducing Test Time of Embedded SRAMs.
MTDT
Baosheng Wang, Josh Yang, André Ivanov
2003 J jnl
Test Technology Technical Council Newsletter.
J. Electron. Test.
André Ivanov
2003 J jnl
Test Technology Technical Council Newsletter.
J. Electron. Test.
André Ivanov
2003 J jnl
Test Technology Technical Council Newsletter.
J. Electron. Test.
André Ivanov
2003 J jnl
Test Technology Technical Council Newsletter.
J. Electron. Test.
André Ivanov
2003 J jnl
Test Technology Technical Council Newsletter.
J. Electron. Test.
André Ivanov
2003 J jnl
Thermal Testing of Analogue Integrated Circuits: A Case Study.
J. Electron. Test.
Josep Altet, André Ivanov, A. Wong
2003 A conf
Time Domain Multiplexed TAM: Implementation and Comparison.
DATE
Zahra Sadat Ebadi, André Ivanov
2003 — conf
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.
Asian Test Symposium
Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov
2002 A conf
An Embedded Core for Sub-Picosecond Timing Measurements.
ITC
Sassan Tabatabaei, André Ivanov
2002 — conf
An Off-Chip Sensor Circuit for On-Line Transient Current Testing.
IOLTW
Bartomeu Alorda, André Ivanov, Jaume Segura
2002 J jnl
CMOS Differential and Absolute Thermal Sensors.
J. Electron. Test.
Ashish Syal, Victor Lee, André Ivanov, Josep Altet
2002 A conf
Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores.
ITC
Mohsen Nahvi, André Ivanov, Resve A. Saleh
2002 — conf
Design of an Optimal Test Access Architecture under Power and Place-and-Route Constraints Using GA.
LATW
Zahra Sadat Ebadi, André Ivanov
2002 J jnl
Embedded Timing Analysis: A SoC Infrastructure.
IEEE Des. Test Comput.
Sassan Tabatabaei, André Ivanov
2002 J jnl
Test Technology Technical Council Newsletter.
J. Electron. Test.
André Ivanov
2002 J jnl
Test Technology Technical Council Newsletter.
J. Electron. Test.
André Ivanov
2002 J jnl
Test Technology Technical Council Newsletter.
J. Electron. Test.
André Ivanov
2001 — conf
A packet switching communication-based test access mechanism for system chips.
ETW
Mohsen Nahvi, André Ivanov
2001 — conf
CMOS Differential and Absolute Thermal Sensors.
IOLTW
Ashish Syal, Victor Lee, André Ivanov, Josep Altet
2001 — conf
Design of an Optimal Test Access Architecture Using a Genetic Algorithm.
Asian Test Symposium
Zahra Sadat Ebadi, André Ivanov
2001 J jnl
On the detectability of CMOS floating gate transistor faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand
2001 J jnl
Test Technology Newsletter.
J. Electron. Test.
André Ivanov
2000 Misc conf
Biomedical ICs: What is Different about Testing those ICs?
VTS
Bapiraju Vinnakota, André Ivanov
2000 J jnl
Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study.
J. Electron. Test.
André Ivanov, Vikram Devdas
2000 — conf
Defect Oriented Testing of an ECL/CMOS Level Converter Circuit.
LATW
Min-Hsing P. Chen, André Ivanov, Sassan Tabatabaei
2000 Misc conf
Do I Need this Tool for My Chips to Work?
VTS
Fidel Muradali, André Ivanov
1999 Misc conf
A Current Integrator for BIST of Mixed-Signal ICs.
VTS
Sassan Tabatabaei, André Ivanov
1999 — conf
A built-in current monitor for testing analog circuit blocks.
ISCAS (2)
Sassan Tabatabaei, André Ivanov
1999 A conf
Optimal conditions for Boolean and current detection of floating gate faults.
ITC
Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq
1998 — conf
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.
Asian Test Symposium
Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand
1998 — conf
Non-Intrusive Testing of High-Speed CML Circuits.
Asian Test Symposium
Vikram Devdas, André Ivanov
1998 — conf
Testing for Floating Gates Defects in CMOS Circuits.
Asian Test Symposium
Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell
1997 — conf
Power supply current monitoring techniques for testing PLLs.
Asian Test Symposium
Maneesha Dalmia, André Ivanov, Sassan Tabatabaei
1996 J jnl
Panel Summaries.
IEEE Des. Test Comput.
Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
1996 J jnl
Programmable BIST Space Compactors.
IEEE Trans. Computers
André Ivanov, Barry K. Tsuji, Yervant Zorian
1995 J jnl
A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes.
J. Electron. Test.
D. Lambidonis, Vinod K. Agarwal, André Ivanov, Dhiren Xavier
1995 J jnl
Fast signature computation for BIST linear compactors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
D. Lambidonis, André Ivanov, Vinod K. Agarwal
1995 C conf
Fault Simulation of an OTA Biquadratic Filter.
ISCAS
Andrew Bishop, André Ivanov
1995 J jnl
Reducing Hardware with Fuzzy Multiple Signature Analysis.
IEEE Des. Test Comput.
Yuejian Wu, André Ivanov
1995 J jnl
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST.
IEEE Trans. Computers
Yuejian Wu, André Ivanov
1994 J jnl
On minimizing aliasing in scan-based compaction.
J. Electron. Test.
Slawomir Pilarski, André Ivanov, Tiko Kameda
1994 — conf
On the Testability of CMOS Feedback Amplifiers.
DFT
Andrew J. Bishop, André Ivanov
1993 Misc conf
Minimal hardware multiple signature analysis for BIST.
VTS
Yuejian Wu, André Ivanov
1993 J jnl
Notes on Multiple Input Signature Analysis.
IEEE Trans. Computers
Tiko Kameda, Slawomir Pilarski, André Ivanov
1993 — conf
Programmable Space Compaction for BIST.
FTCS
Yervant Zorian, André Ivanov
1993 J jnl
Sequential faults and aliasing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Slawomir Pilarski, Tiko Kameda, André Ivanov
1992 Misc conf
Accelerated path delay fault simulation.
VTS
Yuejian Wu, André Ivanov
1992 J jnl
An Effective BIST Scheme for ROM's.
IEEE Trans. Computers
Yervant Zorian, André Ivanov
1992 J jnl
Computing the probability of undetected error for shortened cyclic codes.
IEEE Trans. Commun.
Vinod K. Agarwal, André Ivanov
1992 J jnl
Count-based BIST compaction schemes and aliasing probability computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
André Ivanov, Yervant Zorian
1992 J jnl
Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms.
Integr.
André Ivanov, Slawomir Pilarski
1992 J jnl
Using an asymmetric error model to study aliasing in signature analysis registers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal
1991 A conf
Fast Signature Computation for Linear Compactors.
ITC
D. Lambidonis, André Ivanov, Vinod K. Agarwal
1991 J jnl
Iterative algorithms for computing aliasing probabilities.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
André Ivanov, Corot W. Starke, Vinod K. Agarwal, Wilfried Daehn, Matthias Gruetzner, Tom W. Williams
1990 A conf
Computing the Error Escape Probability in Count-Based Compaction Schemes.
ICCAD
André Ivanov, Yervant Zorian
1990 A conf
EEODM: An effective BIST scheme for ROMs.
ITC
Yervant Zorian, André Ivanov
1989 A conf
: Experiments on Aliasing in Signature Analysis Registers.
ITC
Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal
1989 J jnl
An analysis of the probabilistic behavior of linear feedback signature registers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
André Ivanov, Vinod K. Agarwal
1988 — conf
An iterative technique for calculating aliasing probability of linear feedback signature registers.
FTCS
André Ivanov, Vinod K. Agarwal
1988 J jnl
Dynamic testability measures for ATPG.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
André Ivanov, Vinod K. Agarwal
1988 A conf
On Multiple Fault Coverage and Aliasing Probability Measures.
ITC
Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski
1986 A conf
Testability Measures : What Do They Do for ATPG ?
ITC
André Ivanov, Vinod K. Agarwal