André Inácio Reis

120 papers A 3C 15Journal 24Unranked 76

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Extending Multilevel ALS to Design ATMRs. LASCAS Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2023	—	`conf`	ATMR design by construction based on two-level ALS. SBCCI Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2023	C	`conf`	An Improved method to join BDDs for incompletely specified Boolean functions. ISCAS Renato D. Peralta, Joao P. Nespolo, Paulo F. Butzen, Mariana Kolberg, André Inácio Reis
2023	—	`conf`	Effect of Unique Table Implementation in the Performance of BDD Packages. SBCCI Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis
2023	—	`conf`	Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis. ISVLSI Gabriel Ammes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2023	C	`conf`	Live Demonstration: Pitanga Platform for Virtual FPGA Remote Laboratories. ISCAS Alcides S. Costa, Leonardo Droves Silveira, André Inácio Reis
2022	—	`conf`	A Virtual Board Approach for Prototyping and Teaching Digital Design. SBCCI Alcides S. Costa, Leonardo Droves Silveira, André Inácio Reis
2022	J	`jnl`	Optimizing machine learning logic circuits with constant signal propagation. Integr. Augusto Andre Souza Berndt, Cristina Meinhardt, André Inácio Reis, Paulo F. Butzen
2022	—	`conf`	Possible Reductions to Generate circuits from BDDs. ISVLSI Eduarde D. Brandão, Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis
2020	J	`jnl`	Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas
2020	J	`jnl`	Parallel Combinational Equivalence Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis
2020	J	`jnl`	maj-n Logic Synthesis for Emerging Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Augusto Neutzling, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas
2019	J	`jnl`	Effective Logic Synthesis for Threshold Logic Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Augusto Neutzling, Jody Maick Matos, Alan Mishchenko, André Inácio Reis, Renato P. Ribas
2019	J	`jnl`	Efficiently Mapping VLSI Circuits With Simple Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jody Maick Matos, Jordi Carrabina, André Inácio Reis
2019	J	`jnl`	Four-Level Forms for Memristive Material Implication Logic. IEEE Trans. Very Large Scale Integr. Syst. Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2019	—	`conf`	Reduction of neural network circuits by constant and nearly constant signal propagation. SBCCI Augusto Andre Souza Berndt, Alan Mishchenko, Paulo Francisco Butzen, André Inácio Reis
2018	J	`jnl`	A Simple and Effective Heuristic Method for Threshold Logic Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2018	—	`book`	Advanced Logic Synthesis André Inácio Reis, Rolf Drechsler
2018	—	`conf`	Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas
2018	—	`ch.`	Physical Awareness Starting at Technology-Independent Logic Synthesis. Advanced Logic Synthesis André Inácio Reis, Jody M. A. Matos
2018	C	`conf`	Technology Mapping for Circuits with Simple Cells. ISCAS Jody Maick Matos, André Inácio Reis, Jordi Carrabina
2018	—	`conf`	Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution. ISPD André Inácio Reis
2018	A	`conf`	Unlocking fine-grain parallelism for AIG rewriting. ICCAD Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis
2017	—	`conf`	Binary adder circuit design using emerging MIGFET devices. ISQED Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas
2017	—	`conf`	Contributions to Modeling Patent Claims When Representing Patent Knowledge. AICOL Simone R. N. Reis, André Inácio Reis, Jordi Carrabina, Pompeu Casanovas
2017	—	`conf`	Fast-extract with cube hashing. ASP-DAC Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis
2017	J	`jnl`	SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. IEEE Trans. Emerg. Top. Comput. Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2017	J	`jnl`	Transistor Count Optimization in IG FinFET Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2016	J	`jnl`	Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Júnior
2016	—	`conf`	Performance evaluation of optimized transistor networks built using independent-gate FinFET. LASCAS Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2015	—	`conf`	A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design. ISPD Jody Maick Matos, Augusto Neutzling, Renato P. Ribas, André Inácio Reis
2015	C	`conf`	Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2015	C	`conf`	Enhanced Spin-Diode Synthesis Using Logic Sharing. DSD Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
2015	J	`jnl`	Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. Microelectron. Reliab. Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
2015	J	`jnl`	Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
2015	C	`conf`	Fast buffer delay estimation considering time-dependent dielectric breakdown. ISCAS Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2015	C	`conf`	Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
2015	—	`conf`	Open Cell Library in 15nm FreePDK Technology. ISPD Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen
2015	C	`conf`	SOP based logic synthesis for memristive IMPLY stateful logic. ICCD Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2015	A	`conf`	Threshold Logic Synthesis Based on Cut Pruning. ICCAD Augusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko
2015	—	`conf`	Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. LATS Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
2014	C	`conf`	A constructive approach for threshold logic circuit synthesis. ISCAS Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2014	C	`conf`	CMOS inverter analytical delay model considering all operating regions. ISCAS Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2014	—	`conf`	Deriving Reduced Transistor Count Circuits from AIGs. SBCCI Jody Maick Matos, Marcus Ritt, Renato P. Ribas, André Inácio Reis
2014	—	`conf`	Exploring Independent Gates in FinFET-Based Transistor Network Generation. SBCCI Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Júnior
2014	—	`conf`	Methodology for achieving best trade-off of area and fault masking coverage in ATMR. LATW Iuri A. C. Gomes, Mayler G. A. Martins, Fernanda Lima Kastensmidt, André Inácio Reis, Renato P. Ribas, Sylvain P. Novales
2014	—	`conf`	Optimization on cell-library design for digital Application Specific Printed Electronics Circuits. PATMOS Manuel Llamas, Mohammad Mashayekhi, Jordi Carrabina, Jody Maick Matos, André Inácio Reis
2014	—	`conf`	Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans
2013	—	`conf`	A methodology to evaluate the aging impact on flip-flops performance. SBCCI Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2013	—	`conf`	Analytical logical effort formulation for minimum active area under delay constraints. SBCCI Caio G. P. Alegretti, Vinícius Dal Bem, Renato P. Ribas, André Inácio Reis
2013	J	`jnl`	BTI and HCI first-order aging estimation for early use in standard cell technology mapping. Microelectron. Reliab. Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2013	J	`jnl`	BTI, HCI and TDDB aging impact in flip-flops. Microelectron. Reliab. Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2013	—	`conf`	CMOS inverter delay model based on DC transfer curve for slow input. ISQED Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2013	—	`conf`	Delay model for static CMOS complex gates. SBCCI Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2013	—	`conf`	Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Júnior
2013	—	`conf`	Improving the methodology to build non-series-parallel transistor arrangements. SBCCI Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
2013	—	`conf`	Iterative remapping respecting timing constraints. ISVLSI Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2013	—	`conf`	Logic synthesis for manufacturability considering regularity and lithography printability. ISVLSI Lucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis
2013	—	`conf`	Power consumption analysis in static CMOS gates. SBCCI Alberto Wiltgen, Kim A. Escobar, André Inácio Reis, Renato P. Ribas
2013	—	`conf`	Read-polarity-once Boolean functions. SBCCI Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2013	—	`conf`	Spin diode network synthesis using functional composition. SBCCI Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
2013	—	`conf`	Synthesis of threshold logic gates to nanoelectronics. SBCCI Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2013	—	`conf`	Transistor-level optimization of CMOS complex gates. LASCAS Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2012	J	`jnl`	Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectron. Reliab. Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2012	—	`conf`	Design-oriented delay model for CMOS inverter. SBCCI Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2012	—	`conf`	Functional composition: A new paradigm for performing logic synthesis. ISQED Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
2012	—	`conf`	KL-cut based digital circuit remapping. NORCHIP Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2012	—	`conf`	Lithography analysis of via-configurable transistor-array fabrics. NORCHIP Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2012	—	`conf`	NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2011	—	`conf`	Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2011	—	`conf`	Constructive AIG optimization considering input weights. ISQED Thiago Figueiro, Renato P. Ribas, André Inácio Reis
2011	—	`conf`	Constructive AIG optimization through functional composition. ARCS Workshops Thiago Figueiro, Renato P. Ribas, André Inácio Reis
2011	J	`jnl`	Contributions to the evaluation of ensembles of combinational logic gates. Microelectron. J. Renato P. Ribas, Simone Bavaresco, N. Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André Inácio Reis
2011	—	`conf`	Efficient method to compute minimum decision chains of Boolean functions. ACM Great Lakes Symposium on VLSI Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
2011	C	`conf`	Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2011	—	`conf`	Performance and functional test of flip-flops using ring oscillator structure. IDT Renato P. Ribas, André Inácio Reis, André Ivanov
2011	—	`conf`	Ring oscillators for functional and delay test of latches and flip-flops. SBCCI Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov
2011	—	`conf`	SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. ARCS Workshops Martin Elhøj, André Inácio Reis, Renato P. Ribas, Fabrizio Ferrandi, Christian Pilato, Francesc Moll, Miguel Miranda, Petr Dobrovolný, Nigel Woolaway, Arnaud Grasset, Philippe Bonnot, Giuseppe Desoli, Davide Pandini
2011	C	`conf`	Self-checking test circuits for latches and flip-flops. IOLTS Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov
2011	—	`conf`	Transistor Sizing Analysis of Regular Fabrics. ARCS Workshops Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas, Francesc Moll
2011	—	`conf`	Transistor sizing in lithography-aware regular fabrics. SBCCI Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Francesc Moll, Renato P. Ribas
2010	C	`conf`	Boolean factoring with multi-objective goals. ICCD Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis
2010	J	`jnl`	Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology. Microelectron. Reliab. Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas
2010	—	`conf`	Improvements on the detection of false paths by using unateness and satisfiability. SBCCI Felipe S. Marques, Osvaldo Martinello, Renato P. Ribas, André Inácio Reis
2010	A	`conf`	KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. DATE Osvaldo Martinello, Felipe S. Marques, Renato P. Ribas, André Inácio Reis
2010	J	`jnl`	Karma: um ambiente para o aprendizado de síntese de funções Booleanas. Revista Brasileira de Informática na Educ. Carlos Eduardo Klock, Renato Perez Ribas, André Inácio Reis
2010	J	`jnl`	Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. J. Low Power Electron. Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2010	J	`jnl`	Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. Microelectron. J. Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas
2010	—	`conf`	SwitchCraft: a framework for transistor network design. SBCCI Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Júnior, Renato P. Ribas, André Inácio Reis
2010	J	`jnl`	Transistor network restructuring against NBTI degradation. Microelectron. Reliab. Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2009	J	`jnl`	CMOS logic gate performance variability related to transistor network arrangements. Microelectron. Reliab. Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas
2009	C	`conf`	Efficient Test Circuit to Qualify Logic Cells. ISCAS Renato P. Ribas, Simone Bavaresco, Marcelo Lubaszewski, André Inácio Reis
2009	—	`conf`	Routing Resistance Influence in Loading Effect on Leakage Analysis. PATMOS Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2009	—	`conf`	Switch level optimization of digital CMOS gate networks. ISQED Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis
2009	—	`conf`	What about the IP of your IP?: an introduction to intellectual property law for engineers and scientists. SBCCI André Inácio Reis, Roner G. Fabris
2008	—	`conf`	Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ACM Great Lakes Symposium on VLSI Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas
2008	—	`conf`	Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. ISQED Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis
2007	—	`conf`	A comparative study of CMOS gates with minimum transistor stacks. SBCCI Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider
2007	—	`conf`	DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2007	—	`conf`	KARMA: A Didactic Tool for Two-Level Logic Synthesis. MSE Carlos Eduardo Klock, Felipe Ribeiro Schneider, M. V. N. Gomes, Dionatan S. Moura, Renato P. Ribas, André Inácio Reis
2007	—	`conf`	Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
2007	—	`conf`	Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
2007	—	`conf`	Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
2006	—	`conf`	Asynchronous circuit design on reconfigurable devices. SBCCI R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis
2006	—	`conf`	Fast disjoint transistor networks from BDDs. SBCCI Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2005	—	`conf`	A new approach to the use of satisfiability in false path detection. ACM Great Lakes Symposium on VLSI Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2005	C	`conf`	Exact lower bound for the number of switches in series to implement a combinational logic cell. ICCD Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2005	—	`conf`	Tool integration using the web-services approach. ACM Great Lakes Symposium on VLSI João Daniel Togni, Renato P. Ribas, Maria Lúcia Blanck Lisbôa, André Inácio Reis
2004	—	`conf`	Advanced technology mapping for standard-cell generators. SBCCI Vinícius P. Correia, André Inácio Reis
2004	—	`conf`	Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. SBCCI Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas
2003	—	`conf`	SIFU! - A Didactic Stuck-at Fault Simulator. MSE Vinícius P. Correia, Marcelo Lubaszewski, André Inácio Reis
2003	—	`conf`	Scheduling Policy Costs on a JAVA Microcontroller. OTM Workshops Leomar S. da Rosa Jr., Flávio Rech Wagner, Luigi Carro, Alexandre Carissimi, André Inácio Reis
2003	—	`conf`	Unified Theory to Build Cell-Level Transistor Networks from BDDs. SBCCI Renato E. B. Poli, Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis
2002	—	`conf`	Automatic Generation of Digital Cell Libraries. SBCCI João Daniel Togni, Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis
2002	—	`conf`	Comparing Transistor-Level Implementations of 4-Input Logic Functions. IWLS Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis
2002	—	`conf`	Compression and Technology Mapping of Logic Circuits. SBCCI Vinícius Pazutti Correia, André Inácio Reis
2002	—	`conf`	Testability Properties of BDDs. SBCCI Felipe S. Marques, Vinícius P. Correia, A. Prado, Marcelo Lubaszewski, André Inácio Reis
2001	—	`conf`	A Tutorial Tool for Switch Logic. MSE Vinícius P. Correia, André Inácio Reis
2001	J	`jnl`	Concepção de Circuitos e Sistemas Integrados. RITA Renato P. Ribas, André Inácio Reis, Marcelo Lubaszewski
2000	—	`conf`	Testability Properties of Vertex Precedent BDDs. SBCCI André Inácio Reis, A. Prado, Marcelo Lubaszewski