André DeHon - RankMe

144 papers A* 10A 36B 5C 2Misc 15Journal 38Unranked 33

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds. FPGA Ezra Thomas, Jing Li, André DeHon
2026	A	`conf`	HiLFS: FPGA-Orchestrated File System for High-Level Synthesis. FPGA YoungSeok Na, Linus Y. Wong, André DeHon, Jing Jane Li
2024	J	`jnl`	ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation. ACM Trans. Reconfigurable Technol. Syst. Yuanlong Xiao, Dongjoon Park, Zeyu Jason Niu, Aditya Hota, André DeHon
2024	A	`conf`	REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs. FPGA Dongjoon Park, André DeHon
2023	—	`conf`	Asymmetry in Butterfly Fat Tree FPGA NoC. ICFPT Dongjoon Park, Zhijing Yao, Yuanlong Xiao, André DeHon
2022	—	`conf`	Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration. FPT Dongjoon Park, Yuanlong Xiao, André DeHon
2022	A	`conf`	HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. FPGA Yuanlong Xiao, André DeHon
2022	B	`conf`	HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. FPL Yuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon
2022	A*	`conf`	PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. ASPLOS Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon
2022	J	`jnl`	SCALPEL: Exploring the Limits of Tag-enforced Compartmentalization. ACM J. Emerg. Technol. Comput. Syst. Nick Roessler, André DeHon
2021	Misc	`conf`	Flightplan: Dataplane Disaggregation and Placement for P4 Programs. NSDI Nik Sultana, John Sonchack, Hans Giesen, Isaac Pedisich, Zhaoyang Han, Nishanth Shyamkumar, Shivani Burad, André DeHon, Boon Thau Loo
2021	J	`jnl`	Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems. IEEE Trans. Computers João M. P. Cardoso, André DeHon, Laura Pozzi
2021	Misc	`conf`	HLS-Compatible, Embedded-Processor Stream Links. FCCM Eric Micallef, Yuanlong Xiao, André DeHon
2021	J	`jnl`	Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation. CoRR André DeHon, Hans Giesen, Nik Sultana, Yuanlong Xiao
2021	A*	`conf`	Preventing Dynamic Library Compromise on Node.js via RWX-Based Privilege Reduction. CCS Nikos Vasilakis, Cristian-Alexandru Staicu, Grigoris Ntousakis, Konstantinos Kallas, Ben Karel, André DeHon, Michael Pradel
2021	Misc	`conf`	XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion. FCCM Matthew Hofmann, Zhiyao Tang, Jonathan Orgill, Jonathan Nelson, David Glanzman, Brent Nelson, André DeHon
2021	A	`conf`	μSCOPE: A Methodology for Analyzing Least-Privilege Compartmentalization in Large Software Artifacts. RAID Nick Roessler, Lucas Atayde, Imani Palmer, Derrick Paul McKee, Jai Pandey, Vasileios P. Kemerlis, Mathias Payer, Adam Bates, Jonathan M. Smith, André DeHon, Nathan Dautenhahn
2020	A	`conf`	DeepMatch: practical deep packet inspection in the data plane using network processors. CoNEXT Joel Hypolite, John Sonchack, Shlomo Hershkop, Nathan Dautenhahn, André DeHon, Jonathan M. Smith
2020	—	`conf`	Fast Linking of Separately-Compiled FPGA Blocks without a NoC. FPT Yuanlong Xiao, Syed Tousif Ahmed, André DeHon
2020	J	`jnl`	Introduction to Special Section on FCCM 2019. ACM Trans. Reconfigurable Technol. Syst. André DeHon
2020	J	`jnl`	Mir: Automated Quantifiable Privilege Reduction Against Dynamic Library Compromise in JavaScript. CoRR Nikos Vasilakis, Cristian-Alexandru Staicu, Greg Ntousakis, Konstantinos Kallas, Ben Karel, André DeHon, Michael Pradel
2019	A*	`conf`	Ignis: scaling distribution-oblivious systems with light-touch distribution. PLDI Nikos Vasilakis, Ben Karel, Yash Palkhiwala, John Sonchack, André DeHon, Jonathan M. Smith
2019	—	`conf`	Pipelined Parallel Finite Automata Evaluation. FPT Vipula Sateesh, Connor Mckeon, Jared Winograd, André DeHon
2019	—	`conf`	Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. FPT Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon
2018	A*	`conf`	BreakApp: Automated, Flexible Application Compartmentalization. NDSS Nikos Vasilakis, Ben Karel, Nick Roessler, Nathan Dautenhahn, André DeHon, Jonathan M. Smith
2018	B	`conf`	Case for Fast FPGA Compilation Using Partial Reconfiguration. FPL Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon
2018	J	`jnl`	Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). ACM Trans. Reconfigurable Technol. Syst. Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon
2018	—	`conf`	In-network computing to the rescue of faulty links. NetCompute@SIGCOMM Hans Giesen, Lei Shi, John Sonchack, Anirudh Chelluri, Nishanth Prabhu, Nik Sultana, Latha A. Kant, Anthony J. McAuley, Alexander Poylisher, André DeHon, Boon Thau Loo
2018	A*	`conf`	Protecting the Stack with Metadata Policies and Tagged Hardware. IEEE Symposium on Security and Privacy Nick Roessler, André DeHon
2017	A	`conf`	Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. FPGA Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon
2017	J	`jnl`	Self-Adaptive Timing Repair. IEEE Des. Test Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon
2017	—	`conf`	Towards Fine-grained, Automated Application Compartmentalization. PLOS@SOSP Nikos Vasilakis, Ben Karel, Nick Roessler, Nathan Dautenhahn, André DeHon, Jonathan M. Smith
2016	J	`jnl`	A verified information-flow architecture. J. Comput. Secur. Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Catalin Hritcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach
2016	J	`jnl`	Accurate Parallel Floating-Point Accumulation. IEEE Trans. Computers Edin Kadric, Paul Gurniak, André DeHon
2016	Misc	`conf`	Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). FCCM Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon
2016	Misc	`conf`	Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. FCCM Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, André DeHon
2016	J	`jnl`	Impact of Parallelism and Memory Architecture on FPGA Communication Energy. ACM Trans. Reconfigurable Technol. Syst. Edin Kadric, David Lakata, André DeHon
2016	J	`jnl`	Introduction to Special Issue on Reconfigurable Components with Source Code. ACM Trans. Reconfigurable Technol. Syst. André DeHon, Derek Chiou
2016	—	`conf`	PERFECT case studies demonstrating order of magnitude reduction in power consumption. HPEC David K. Wittenberg, Edin Kadric, André DeHon, Jonathan Edwards, Jeffrey Smith, Silviu Chiricescu
2016	A	`conf`	Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement. FPGA Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, André DeHon
2015	J	`jnl`	A Verified Information-Flow Architecture. CoRR Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Catalin Hritcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach
2015	A*	`conf`	Architectural Support for Software-Defined Metadata Processing. ASPLOS Udit Dhawan, Catalin Hritcu, Raphael Rubin, Nikos Vasilakis, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon
2015	J	`jnl`	Area-Efficient Near-Associative Memories on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Udit Dhawan, André DeHon
2015	—	`conf`	Energy minimization in the time-space continuum. FPT Hyunseok Park, Shreel Vijayvargiya, André DeHon
2015	J	`jnl`	Fundamental Underpinnings of Reconfigurable Computing Architectures. Proc. IEEE André DeHon
2015	J	`jnl`	GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction. ACM Trans. Reconfigurable Technol. Syst. Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon
2015	A	`conf`	Impact of Memory Architecture on FPGA Energy Consumption. FPGA Edin Kadric, David Lakata, André DeHon
2015	J	`jnl`	Reconfigurable Computing Architectures. Proc. IEEE Russell Tessier, Kenneth L. Pocek, André DeHon
2014	A*	`conf`	A verified information-flow architecture. POPL Arthur Azevedo de Amorim, Nathan Collins, André DeHon, Delphine Demange, Catalin Hritcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach
2014	Misc	`conf`	Energy Reduction through Differential Reliability and Lightweight Checking. FCCM Edin Kadric, Kunal Mahajan, André DeHon
2014	Misc	`conf`	GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction. FCCM Benjamin Gojman, André DeHon
2014	Misc	`conf`	Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations. FCCM Edin Kadric, Kunal Mahajan, André DeHon
2014	—	`conf`	PUMP: a programmable unit for metadata processing. HASP@ISCA Udit Dhawan, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon
2014	—	`conf`	RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks. FPT Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith, André DeHon
2014	A	`conf`	Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization. FPGA André DeHon
2013	C	`conf`	Accurate Parallel Floating-Point Accumulation. IEEE Symposium on Computer Arithmetic Edin Kadric, Paul Gurniak, André DeHon
2013	A	`conf`	Area-efficient near-associative memories on FPGAs. FPGA Udit Dhawan, André DeHon
2013	—	`conf`	Exploiting partially defective LUTs: Why you don't need perfect fabrication. FPT André DeHon, Nikil Mehta
2013	A	`conf`	GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction. FPGA Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon
2013	A	`conf`	Location, location, location: the role of spatial locality in asymptotic energy minimization. FPGA André DeHon
2013	A*	`conf`	Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security. CCS Albert Kwon, Udit Dhawan, Jonathan M. Smith, Thomas F. Knight Jr., André DeHon
2012	J	`jnl`	${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nachiket Kapre, André DeHon
2012	—	`conf`	FPGA optimized packet-switched NoC using split and merge primitives. FPT Yutian Huan, André DeHon
2012	—	`conf`	Hardware Support for Safety Interlocks and Introspection. SASO Workshops Udit Dhawan, Albert Kwon, Edin Kadric, Catalin Hritcu, Benjamin C. Pierce, Jonathan M. Smith, André DeHon, Gregory Malecha, Greg Morrisett, Thomas F. Knight Jr., Andrew Sutherland, Tom Hawkins, Amanda Zyxnfryx, David K. Wittenberg, Peter Trei, Sumit Ray, Greg Sullivan
2012	A	`conf`	Limit study of energy & delay benefits of component-specific routing. FPGA Nikil Mehta, Raphael Rubin, André DeHon
2011	J	`jnl`	An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads. Int. J. Reconfigurable Comput. Nachiket Kapre, André DeHon
2011	J	`jnl`	Choose-your-own-adventure routing: Lightweight load-time defect avoidance. ACM Trans. Reconfigurable Technol. Syst. Raphael Rubin, André DeHon
2011	—	`ch.`	Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. Low-Power Variation-Tolerant Design in Nanometer Silicon Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon
2011	J	`jnl`	Crystals and Snowflakes: Building Computation from Nanowire Crossbars. Computer André DeHon, Benjamin Gojman
2011	—	`ch.`	Low-Power Techniques for FPGAs. Low-Power Variation-Tolerant Design in Nanometer Silicon Nikil Mehta, André DeHon
2011	—	`conf`	Preliminary design of the SAFE platform. PLOS@SOSP André DeHon, Ben Karel, Thomas F. Knight Jr., Gregory Malecha, Benoît Montagu, Robin Morisset, Greg Morrisett, Benjamin C. Pierce, Randy Pollack, Sumit Ray, Olin Shivers, Jonathan M. Smith, Gregory Sullivan
2011	J	`jnl`	Spatial hardware implementation for sparse graph algorithms in GraphStep. ACM Trans. Auton. Adapt. Syst. Michael DeLorimier, Nachiket Kapre, Nikil Mehta, André DeHon
2011	A	`conf`	Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder. FPGA Raphael Rubin, André DeHon
2011	—	`conf`	VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. FPT Nachiket Kapre, André DeHon
2011	—	`ch.`	Variation and Aging Tolerance in FPGAs. Low-Power Variation-Tolerant Design in Nanometer Silicon Nikil Mehta, André DeHon
2010	—	`conf`	An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications. ReCoSoC Nachiket Kapre, André DeHon
2010	A	`conf`	Vision for cross-layer optimization to address the dual challenges of energy and reliability. DATE André DeHon, Heather M. Quinn, Nicholas P. Carter
2009	Misc	`conf`	Accelerating SPICE Model-Evaluation using FPGAs. FCCM Nachiket Kapre, André DeHon
2009	A	`conf`	CMOS vs Nano: comrades or rivals? FPGA Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger
2009	A	`conf`	Choose-your-own-adventure routing: lightweight load-time defect avoidance. FPGA Raphael Rubin, André DeHon
2009	J	`jnl`	Fault Secure Encoder and Decoder for NanoMemory Applications. IEEE Trans. Very Large Scale Integr. Syst. Helia Naeimi, André DeHon
2009	J	`jnl`	Inversion schemes for sublithographic programmable logic arrays. IET Comput. Digit. Tech. Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon
2009	B	`conf`	Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. FPL Nachiket Kapre, André DeHon
2009	J	`jnl`	Pipelining Saturated Accumulation. IEEE Trans. Computers Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon
2009	—	`conf`	VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems. FPT Benjamin Gojman, André DeHon
2008	J	`jnl`	Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs. ACM Trans. Reconfigurable Technol. Syst. André DeHon, Mike Hutton
2007	—	`conf`	06361 Abstracts Collection -- Computing Media Languages for Space-Oriented Computation. Computing Media and Languages for Space-Oriented Computation André DeHon, Jean-Louis Giavitto, Frédéric Gruau
2007	—	`conf`	06361 Executive Report -- Computing Media Languages for Space-Oriented Computation. Computing Media and Languages for Space-Oriented Computation André DeHon, Jean-Louis Giavitto, Frédéric Gruau
2007	—	`conf`	Architecture approaching the atomic scale. ESSCIRC André DeHon
2007	—	`ed.`	Computing Media and Languages for Space-Oriented Computation, 03.09. - 08.09.2006 Computing Media and Languages for Space-Oriented Computation André DeHon, Jean-Louis Giavitto, Frédéric Gruau
2007	—	`conf`	Fault Secure Encoder and Decoder for Memory Applications. DFT Helia Naeimi, André DeHon
2007	—	`conf`	Fault tolerant nano-memory with fault secure encoder and decoder. Nano-Net Helia Naeimi, André DeHon
2007	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kia Bazargan, André DeHon
2007	J	`jnl`	Introduction to the Special Section on Nano Systems and Computing. IEEE Trans. Computers André DeHon, Craig S. Lent, Fabrizio Lombardi
2007	C	`conf`	Optimistic Parallelization of Floating-Point Accumulation. IEEE Symposium on Computer Arithmetic Nachiket Kapre, André DeHon
2007	A	`ed.`	Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007 FPGA André DeHon, Mike Hutton
2006	—	`conf`	3D Nanowire-Based Programmable Logic. Nano-Net Benjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto
2006	Misc	`conf`	GraphStep: A System Architecture for Sparse-Graph Algorithms. FCCM Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomás E. Uribe, Thomas F. Knight Jr., André DeHon
2006	—	`conf`	Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. Nano-Net Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon
2006	Misc	`conf`	Packet Switched vs. Time Multiplexed FPGA Overlay Networks. FCCM Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon
2006	A	`ed.`	Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006 FPGA Steven J. E. Wilton, André DeHon
2006	J	`jnl`	Radial addressing of nanowires. ACM J. Emerg. Technol. Comput. Syst. John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, Yue Wu
2006	—	`conf`	SAT-based optimal hypergraph partitioning with replication. ASP-DAC Michael G. Wrighton, André DeHon
2006	J	`jnl`	Stochastic spatial routing for reconfigurable networks. Microprocess. Microsystems André DeHon, Randy Huang, John Wawrzynek
2006	J	`jnl`	Stream computations organized for reconfigurable execution. Microprocess. Microsystems André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
2006	—	`conf`	Tutorial 1: Emerging Technologies for VLSI Design. ISQED Rajiv V. Joshi, Kaustav Banerjee, André DeHon
2005	A	`conf`	Design of programmable interconnect for sublithographic programmable logic arrays. FPGA André DeHon
2005	A	`conf`	Floating-point sparse matrix-vector multiply for FPGAs. FPGA Michael DeLorimier, André DeHon
2005	A	`conf`	Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. ICCAD André DeHon, Konstantin Likharev
2005	J	`jnl`	Nanowire-based programmable architectures. ACM J. Emerg. Technol. Comput. Syst. André DeHon
2005	—	`conf`	Pipelining Saturated Accumulation. FPT Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon
2005	J	`jnl`	Seven Strategies for Tolerating Highly Defective Fabrication. IEEE Des. Test Comput. André DeHon, Helia Naeimi
2004	—	`conf`	A greedy algorithm for tolerating defective crosspoints in nanoPLA design. FPT Helia Naeimi, André DeHon
2004	Misc	`conf`	Design Patterns for Reconfigurable Computing. FCCM André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton
2004	J	`jnl`	Design of FPGA interconnect for multilevel metallization. IEEE Trans. Very Large Scale Integr. Syst. André DeHon, Raphael Rubin
2004	A	`conf`	Nanowire-based sublithographic programmable logic arrays. FPGA André DeHon, Michael J. Wilson
2004	J	`jnl`	Unifying mesh- and tree-based programmable interconnect. IEEE Trans. Very Large Scale Integr. Syst. André DeHon
2004	A	`conf`	What is the right model for programming and using modern FPGAs? FPGA André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica
2003	A	`conf`	Design of FPGA interconnect for multilevel metalization. FPGA Raphael Rubin, André DeHon
2003	A	`conf`	Hardware-assisted simulated annealing with application for fast FPGA placement. FPGA Michael G. Wrighton, André DeHon
2003	A	`conf`	Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA Randy Huang, John Wawrzynek, André DeHon
2002	A	`conf`	Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon
2002	Misc	`conf`	Hardware-Assisted Fast Routing. FCCM André DeHon, Randy Huang, John Wawrzynek
2002	A	`conf`	Molecular electronics: devices, systems and tools for gigagate, gigabit chips. ICCAD Michael Butts, André DeHon, Seth Copen Goldstein
2002	—	`conf`	Very Large Scale Spatial Computing. UMC André DeHon
2001	—	`conf`	Rent's rule based switching requirements. SLIP André DeHon
2000	B	`conf`	Compact, multilayer layout for butterfly fat-tree. SPAA André DeHon
2000	B	`conf`	Stream Computations Organized for Reconfigurable Execution (SCORE). FPL Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon
2000	J	`jnl`	The Density Advantage of Configurable Computing. Computer André DeHon
1999	A	`conf`	Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization). FPGA André DeHon
1999	A	`conf`	HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon
1999	A*	`conf`	Reconfigurable Computing: What, Why, and Implications for Design Automation. DAC André DeHon, John Wawrzynek
1998	A	`conf`	Fast Module Mapping and Placement for Datapaths in FPGAs. FPGA Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek
1998	J	`jnl`	High Performance, Point-to-Point, Transmission Line Signaling. VLSI Design André DeHon, Thomas F. Knight Jr.
1998	Misc	`conf`	Object Oriented Circuit-Generators in Java. FCCM Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek
1997	—	`conf`	Directions in General-Purpose Computing Architectures. HICSS (1) André DeHon
1997	J	`jnl`	Seeking Solutions in Configurable Computing. Computer William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
1996	A	`conf`	DPGA Utilization and Application. FPGA André DeHon
1996	A	`conf`	Entropy, Counting, and Programmable Interconnect. FPGA André DeHon
1996	Misc	`conf`	MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. FCCM Ethan Mirsky, André DeHon
1996	—	`—`	Reconfigurable architectures for general-purpose computing. André DeHon
1994	—	`conf`	Guaranteeing Idempotence for Tightly-Coupled, Fault-Tolerant Networks. PCRCW Ian Eslick, André DeHon, Thomas F. Knight Jr.
1994	A	`conf`	In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports. ITC André DeHon
1994	A*	`conf`	METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. ISCA Frederic T. Chong, Henry Minsky, André DeHon, Matthew E. Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.