Andrzej Pulka

20 papers A 1B 1C 3Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2025 B conf
Effective Detection and Recognition of Traffic Signs with Light Convolutional Neural Networks.
KES
Maciej Olszewski, Bozena Malysiak-Mrozek, Krzysztof Tokarz, Boleslaw Pochopien, Che-Lun Hung, Andrzej Pulka, Dariusz Mrozek
2023 J jnl
Validation of Task Scheduling Techniques in Multithread Time Predictable Systems.
IEEE Access
Ernest Antolak, Andrzej Pulka
2021 J jnl
Energy-Efficient Task Scheduling in Design of Multithread Time Predictable Real-Time Systems.
IEEE Access
Ernest Antolak, Andrzej Pulka
2020 J jnl
Digitally programmable modified current differencing transconductance amplifier in 40-nm technology: design flow, parameter analyses and applications.
IET Circuits Devices Syst.
Andrzej Malcher, Adam Kristof, Andrzej Pulka
2020 J jnl
Flexible hardware approach to multi-core time-predictable systems design based on the interleaved pipeline processing.
IET Circuits Devices Syst.
Ernest Antolak, Andrzej Pulka
2016 J jnl
Preface.
Microprocess. Microsystems
Andrzej Pulka
2014 J jnl
Selection of search strategies for solving 3-SAT problems.
Int. J. Appl. Math. Comput. Sci.
Andrzej Pulka
2013 — conf
Analysis of timing resources for highly predictable real-time systems models.
MIXDES
Lukasz Golly, Andrzej Pulka
2012 — conf
Dynamic rescheduling of tasks in time predictable embedded systems.
PDeS
Andrzej Pulka, Adam Milik
2011 — conf
Automatic implementation of arithmetic operation in reconfigurable logic controllers.
ECCTD
Adam Milik, Andrzej Pulka
2010 — conf
On efficient implementation of search algorithm for genome patterns.
PDeS
Adam Milik, Andrzej Pulka
2009 — conf
A heterogenous approach to symbolic calculations based on structural numbers.
ICECS
Andrzej Pulka, Lukasz Golly
2009 — conf
Multithread RISC architecture based on programmable interleaved pipelining.
ICECS
Andrzej Pulka, Adam Milik
2009 — conf
The reconfigurable hardware accelerator for searching genome patterns.
PDeS
Adam Milik, Andrzej Pulka
2008 C conf
VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams.
FDL
Andrzej Pulka, Adam Milik
2007 — conf
A Heuristic Fault Dictionary Reduction Methodology.
ICECS
Andrzej Pulka
2007 — conf
A common-sense based approach to the automated test-point selection in fault diagnosis.
ECCTD
Andrzej Pulka, Jerzy Rutkowski
2007 C conf
Common HDL-Matlab Simulation Environment.
FDL
Adam Milik, Andrzej Pulka
2006 C conf
SystemC models generation based on libraries of templates.
ISCAS
Andrzej Pulka
1999 A conf
Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique.
DATE
Jerzy J. Dabrowski, Andrzej Pulka