Andrzej Pfitzner

11 papers C 3Journal 1Unranked 7

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Study of Storage Capacity of Charge Trap EAROM NAND Memory Designed for Integration with VeSTIC Technology. MIXDES Bartosz Dec, Andrzej Pfitzner
2018	—	`conf`	Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology. MIXDES Bartosz Dec, Andrzej Pfitzner
2018	—	`conf`	Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology. MIXDES Mikolaj Palgan, Andrzej Pfitzner
2016	—	`conf`	Contribution to scaling of Vertical-Slit Field-Effect Transistor (VeSFET). MIXDES Andrzej Pfitzner, Beata Kowalska
2015	—	`conf`	Compact DC model of a JVeSFET transistor with reduced number of empirical parameters. MIXDES Michal Staniewski, Andrzej Pfitzner
2014	—	`conf`	Improved simple DC model of Vertical-Slit Field-Effect Transistor (VeSFET). MIXDES Andrzej Pfitzner
2014	—	`conf`	Usefulness of VeSTIC devices for low-noise and radiation hard 3D integrated circuits. MIXDES Michal Staniewski, Andrzej Pfitzner
2012	C	`conf`	Vertical Slit Transistor based Integrated Circuits (VeSTICs). DDECS Andrzej Pfitzner
2009	C	`conf`	Adder Circuits with Transistors using Independently Controlled Gates. ISCAS Marcus Weis, Andrzej Pfitzner, Dominik Kasprowicz, Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel
2008	C	`conf`	Is there always performance overhead for regular fabric? ICCD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
2005	J	`jnl`	Evaluation of parasitic capacitances for interconnection buses crossing in different layers. Microelectron. Reliab. Adam Jarosz, Andrzej Pfitzner