Andrzej Krasniewski

40 papers A* 3A 3B 5C 14Misc 2Journal 4Unranked 9

Year	Rank	Type	Title / Venue / Authors
2014	C	`conf`	Rule Induction Based on Logic Synthesis Methods. ICSEng Grzegorz Borowik, Andrzej Krasniewski, Tadeusz Luba
2012	C	`conf`	Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching. DDECS Jakub Korczyc, Andrzej Krasniewski
2011	C	`conf`	A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs. ICSEng Grzegorz Borowik, Andrzej Krasniewski
2011	—	`conf`	Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs. EUROCAST (2) Grzegorz Borowik, Andrzej Krasniewski
2008	C	`conf`	Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs. DDECS Andrzej Krasniewski
2008	C	`conf`	Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs. DSD Andrzej Krasniewski
2008	J	`jnl`	Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs. Microprocess. Microsystems Andrzej Krasniewski
2007	C	`conf`	Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs. DSD Andrzej Krasniewski
2007	C	`ed.`	Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007 DDECS Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino
2006	C	`conf`	Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs. DDECS Andrzej Krasniewski
2005	C	`conf`	A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. IOLTS Andrzej Krasniewski
2004	—	`conf`	Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs. DFT Andrzej Krasniewski
2004	C	`conf`	Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks. IOLTS Andrzej Krasniewski
2004	B	`conf`	Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. FPL Andrzej Krasniewski
2003	B	`conf`	Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. FPL Andrzej Krasniewski
2003	J	`jnl`	Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs. J. Syst. Archit. Andrzej Krasniewski
2003	C	`conf`	Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption. IOLTS Andrzej Krasniewski
2002	B	`conf`	Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. FPL Andrzej Krasniewski
2002	B	`conf`	On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. FPL Andrzej Krasniewski
2001	C	`conf`	Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. DSD Andrzej Krasniewski
2001	—	`conf`	Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing. IOLTW Andrzej Krasniewski
2000	B	`conf`	Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. FPL Andrzej Krasniewski
2000	—	`conf`	Self-Testing of FPGA Delay Faults in the System Environment. IOLTW Andrzej Krasniewski
1999	—	`conf`	Application-Dependent Testing of FPGA Delay Faults. EUROMICRO Andrzej Krasniewski
1999	—	`conf`	Self-Testing of S-Compatible Test Units in User-Programmed FPGAs. EUROMICRO Pawel Tomaszewicz, Andrzej Krasniewski
1996	Misc	`conf`	Design of Dependable Hardware: What BIST is most Efficient? EDCC Andrzej Krasniewski
1994	Misc	`conf`	Coverage of Delay Faults: When 13% and 99% Mean the Same. EDCC Andrzej Krasniewski, Leszek B. Wronski
1994	—	`conf`	Tests for path delay faults vs. tests for gate delay faults: how different they are. EURO-DAC Andrzej Krasniewski, Leszek B. Wronski
1992	C	`conf`	Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion. ICCD Xiaodong Xie, Alexander Albicki, Andrzej Krasniewski
1992	J	`jnl`	Estimating testing effectiveness of the circular self-test path technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Slawomir Pilarski, Andrzej Krasniewski, Tiko Kameda
1992	A	`conf`	High Quality Testing of Embedded RAMs Using Circular Self-Test Path. ITC Andrzej Krasniewski, Slawomir Pilarski
1991	A	`conf`	Can Redundancy Enhance Testability? ITC Andrzej Krasniewski
1991	A*	`conf`	Logic Synthesis for Efficient Pseudoexhaustive Testability. DAC Andrzej Krasniewski
1991	C	`conf`	Random Testability of Redundant Circuits. ICCD Andrzej Krasniewski, Alexander Albicki
1990	—	`conf`	Design for verification testability. EURO-DAC Andrzej Krasniewski
1989	J	`jnl`	Circular self-test path: a low-cost BIST technique for VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrzej Krasniewski, Slawomir Pilarski
1987	A*	`conf`	Circular Self-Test Path: A Low-Cost BIST Technique. DAC Andrzej Krasniewski, Slawomir Pilarski
1985	A	`conf`	Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. ITC Andrzej Krasniewski, Alexander Albicki
1985	A*	`conf`	Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. DAC Andrzej Krasniewski, Alexander Albicki
1984	—	`conf`	Fuzzy Automata as Adaptive Algorithms for Telephone Traffic Routing. ICC (1) Andrzej Krasniewski