Andrzej J. Strojwas

73 papers A* 18A 12C 2Misc 5Journal 25Unranked 11

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	In-Product BTI Aging Sensor for Reliability Screening and Early Detection of Material at Risk. IRPS Tomasz Brozek, Alberto A. P. Cattaneo, Larg Weiland, Michele Quarantelli, Alberto Coccoli, Sharad Saxena, Christopher Hess, Andrzej J. Strojwas
2019	—	`conf`	Yield and Reliability Challenges at 7nm and Below. MIXDES Andrzej J. Strojwas, Kelvin Doong, Dennis J. Ciplickas
2016	Misc	`conf`	Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below. VTS Andrzej J. Strojwas, Jacob A. Abraham, Hong Hao, Max M. Shulaker
2014	A	`conf`	Sub-20 nm design technology co-optimization for standard cell logic. ICCAD Kaushik Vaidyanathan, Lars Liebmann, Andrzej J. Strojwas, Larry T. Pileggi
2013	A*	`conf`	Automatic clustering of wafer spatial signatures. DAC Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
2013	J	`jnl`	Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
2011	C	`conf`	Cost effective scaling to 22nm and below technology nodes. DDECS Andrzej J. Strojwas
2010	J	`jnl`	Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi, Andrzej J. Strojwas, Jason Hibbeler
2010	A*	`conf`	Who solves the variability problem? DAC Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger
2009	A*	`conf`	Creating an affordable 22nm node using design-lithography co-optimization. DAC Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi
2007	A	`conf`	DFM/DFY: should you trust the surgeon or the family doctor? DATE Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki
2005	A*	`conf`	Correlation-aware statistical timing analysis with non-gaussian delay distributions. DAC Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma
2005	A*	`conf`	Design methodology for IC manufacturability based on regular logic-bricks. DAC V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi
2005	J	`jnl`	Guest Editors' Introduction: DFM Drives Changes in Design Flow. IEEE Des. Test Comput. Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly
2005	A	`conf`	Projection-based performance modeling for inter/intra-die variations. ICCAD Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas
2005	—	`conf`	Statistical Critical Path Analysis Considering Correlations. PATMOS Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark
2005	A	`conf`	Statistical critical path analysis considering correlations. ICCAD Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark
2005	—	`conf`	Tutorial on DFM for physical design. ISPD Andrzej J. Strojwas
2004	A*	`conf`	Routing architecture exploration for regular fabrics. DAC V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi
2003	—	`conf`	Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2003	A*	`conf`	Exploring regular fabrics to optimize the performance-cost trade-off. DAC Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, Kim Yaw Tong
2003	J	`jnl`	Global and local congestion optimization in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002	A	`conf`	Congestion-Aware Logic Synthesis. DATE Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002	—	`conf`	Understanding and addressing the impact of wiring congestion during technology mapping. ISPD Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2001	J	`jnl`	Path delay fault diagnosis and coverage-a metric and an estimationtechnique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mukund Sivaraman, Andrzej J. Strojwas
2000	—	`conf`	Design for manufacturability: a path from system level to high yielding chips: embedded tutorial. ASP-DAC Andrzej J. Strojwas
2000	A	`conf`	Design-Manufacturing Interface for 0.13 Micron and Below. ICCAD Andrzej J. Strojwas
2000	—	`conf`	Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? ISQED Carlo Guardiani, Andrzej J. Strojwas
2000	A*	`conf`	Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas
2000	J	`jnl`	Perspectives on technology and technology-driven CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert W. Dutton, Andrzej J. Strojwas
2000	J	`jnl`	Primitive path delay faults: identification and their use in timinganalysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mukund Sivaraman, Andrzej J. Strojwas
2000	A*	`conf`	When bad things happen to good chips (panel session). DAC N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
1999	Misc	`conf`	A New Methodology for Concurrent Technology Development and Cell Library Optimization. VLSI Design Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, Purnendu K. Mozumder, Andrzej J. Strojwas
1999	J	`jnl`	An algorithm for determining repetitive patterns in very large IC layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
1999	A*	`conf`	Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. DAC Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
1998	—	`conf`	A pattern matching algorithm for verification and analysis of very large IC layouts. ISPD Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
1997	Misc	`conf`	Primitive Path Delay Fault Identification. VLSI Design Mukund Sivaraman, Andrzej J. Strojwas
1997	A	`conf`	Timing analysis based on primitive path delay fault identification. ICCAD Mukund Sivaraman, Andrzej J. Strojwas
1996	Misc	`conf`	A diagnosability metric for parametric path delay faults. VTS Mukund Sivaraman, Andrzej J. Strojwas
1996	A	`conf`	Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. ICCAD Mukund Sivaraman, Andrzej J. Strojwas
1996	Misc	`conf`	Diagnosis of parametric path delay faults. VLSI Design Mukund Sivaraman, Andrzej J. Strojwas
1996	A	`conf`	Manufacturability of low power CMOS technology solutions. ISLPED Andrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, Germano Nicollini, G. Crisenza, Bruno Franzini, J. Wiart
1995	A	`conf`	Test Vector Generation for Parametric Path Delay Faults. ITC Mukund Sivaraman, Andrzej J. Strojwas
1994	A*	`conf`	MONSTR: A Complete Thermal Simulator of Electronic Systems. DAC Vladimir A. Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director
1994	C	`conf`	Stochastic Interpolation Model Scheme for Statistical Circuit Design. ISCAS Jin-Qin Lu, Kimihiro Ogawa, Takehiko Adachi, Andrzej J. Strojwas
1994	—	`conf`	Towards Incorporating Device Parameter Variations in Timing Analysis. EDAC-ETC-EUROASIC Mukund Sivaraman, Andrzej J. Strojwas
1994	—	`conf`	Variable Accuracy Device Modeling for Event-Driven Circuit Simulation. EDAC-ETC-EUROASIC Kimon W. Michaels, Andrzej J. Strojwas
1993	J	`jnl`	Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas
1993	J	`jnl`	The CDB/HCDB semiconductor wafer representation server. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas
1992	A	`conf`	A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. ICCAD Kimon W. Michaels, Andrzej J. Strojwas
1991	A*	`conf`	A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. DAC D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas
1991	J	`jnl`	An efficient algorithm for parametric fault simulation of monolithic IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrzej J. Strojwas, Stephen W. Director
1991	J	`jnl`	Numerical integral method for diffusion modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaowei Tian, Andrzej J. Strojwas
1991	A*	`conf`	The Role of Timing Verification in Layout Synthesis. DAC Jacques Benkoski, Andrzej J. Strojwas
1991	A*	`conf`	Utilizing Logic Information in Multi-Level Timing Simulation. DAC Marko P. Chew, Andrzej J. Strojwas
1990	J	`jnl`	Statistical control of VLSI fabrication processes. Proc. IEEE Purnendu K. Mozumder, Andrzej J. Strojwas
1989	A	`conf`	Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. ITC Jacques Benkoski, Andrzej J. Strojwas
1989	A*	`conf`	Design for Manufacturability and Yield. DAC Andrzej J. Strojwas
1989	A*	`conf`	Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. DAC Jacques Benkoski, Andrzej J. Strojwas
1988	J	`jnl`	The process engineer's workbench. IEEE J. Solid State Circuits Andrzej J. Strojwas, Stephen W. Director
1987	J	`jnl`	A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ihao Chen, Andrzej J. Strojwas
1987	J	`jnl`	A New Approach to Hierarchical and Statistical Timing Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jacques Benkoski, Andrzej J. Strojwas
1987	J	`jnl`	Realistic Yield Simulation for VLSIC Structural Failures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ihao Chen, Andrzej J. Strojwas
1986	J	`jnl`	A Methodology for Worst-Case Analysis of Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
1986	J	`jnl`	A Statistical Design Rule Developer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rahul Razdan, Andrzej J. Strojwas
1986	J	`jnl`	The CMU-CAM System. IEEE Des. Test Andrzej J. Strojwas
1986	J	`jnl`	VLSI Yield Prediction and Estimation: A Unified Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director
1986	A*	`conf`	Yield of VLSI circuits: myths vs. reality (panel). DAC Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper
1985	J	`jnl`	A Pattern Recognition Based Method for IC Failure Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrzej J. Strojwas, Stephen W. Director
1985	A*	`conf`	CMU-CAM system. DAC Andrzej J. Strojwas
1985	J	`jnl`	PROD: A VLSI Fault Diagnosis System. IEEE Des. Test Peter Odryna, Andrzej J. Strojwas
1984	J	`jnl`	FABRICS II: A Statistically Based IC Fabrication Process Simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
1982	J	`jnl`	Statistical Simulation of the IC Manufacturing Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wojciech Maly, Andrzej J. Strojwas