Andrzej Hlawiczka

24 papers B 2C 6Misc 3Journal 5Unranked 8
YearRankTypeTitle / Venue / Authors
2010 C conf
How to reduce size of a signature-based diagnostic dictionary used for testing of connections.
DDECS
Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2010 — conf
Reduced-size signature-based diagnostic dictionary for interconnection testing.
PDeS
Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2009 C conf
Effective BIST for crosstalk faults in interconnects.
DDECS
Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2008 C conf
Interconnect Faults Identification and Localization Using Modified Ring LFSRs.
DDECS
Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec
2007 C conf
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.
DDECS
Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka
2007 C conf
Test Pattern Generator for Delay Faults.
DDECS
Tomasz Rudnicki, Andrzej Hlawiczka
2006 C conf
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor.
DDECS
Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka
2006 B conf
Test-per-Clock Detection, Localization and Identification of Interconnect Faults.
ETS
Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
2004 J jnl
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.
J. Electron. Test.
Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa
2002 — conf
Dependable testing of compactor MISR: an imperceptible problem?
ETW
Andrzej Hlawiczka, Michal Kopec
2002 J jnl
Efficient test pattern generators based on specific cellular automata structures.
Microelectron. Reliab.
Tomasz Garbolino, Andrzej Hlawiczka
2000 — conf
Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.
Asian Test Symposium
Andrzej Hlawiczka, Michal Kopec
2000 — conf
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path.
ETW
Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof
1999 Misc conf
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits.
EDCC
Tomasz Garbolino, Andrzej Hlawiczka
1997 Misc conf
A linear code-preserving signature analyzer COPMISR.
VTS
Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan
1997 — conf
Low Cost Bist for Edac Circuits.
Asian Test Symposium
Dariusz Badura, Andrzej Hlawiczka
1996 Misc ed.
Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings
EDCC
Andrzej Hlawiczka, João Gabriel Silva, Luca Simoncini
1994 B conf
Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures.
FPL
Andrzej Hlawiczka, Jacek Binda
1992 J jnl
Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks.
IEEE Trans. Computers
Andrzej Hlawiczka
1989 — conf
Signature Analysis Testing with Bottom-Top Exclusive Or Type MISR.
Fehlertolerierende Rechensysteme
Andrzej Hlawiczka
1987 — conf
Universal Test Controller Chip for Board Self Test.
Fehlertolerierende Rechensysteme
Andrzej Hlawiczka, Dariusz Badura
1986 J jnl
Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer.
IEEE Trans. Computers
Andrzej Hlawiczka
1984 — conf
Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer.
Fehlertolerierende Rechensysteme
Andrzej Hlawiczka
1978 J jnl
Comments on "Procedures for Eliminating Static and Dynamic-Hazards in Test Generation".
IEEE Trans. Computers
Andrzej Hlawiczka