Andrew R. Pleszkun

26 papers A* 16B 1Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2003 — conf
A Performance Analysis of the iSCSI Protocol.
IEEE Symposium on Mass Storage Systems
Stephen Aiken, Dirk Grunwald, Andrew R. Pleszkun, Jesse Willek
1998 A* conf
Confidence Estimation for Speculation Control.
ISCA
Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun
1998 — conf
Implementation of Precise Interupts in Pipelined Processors.
25 Years ISCA: Retrospectives and Reprints
James E. Smith, Andrew R. Pleszkun
1997 J jnl
Managing data caches using selective cache line replacement.
Int. J. Parallel Program.
Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
1997 A* ed.
Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997
ISCA
Andrew R. Pleszkun, Trevor N. Mudge
1995 A* conf
A modified approach to data cache management.
MICRO
Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
1994 A* conf
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors.
ISCA
Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
1994 A* conf
Techniques for compressing program address traces.
MICRO
Andrew R. Pleszkun
1992 A* conf
MISC: a Multiple Instruction Stream Computer.
MICRO
Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
1991 J jnl
Implementation of the PIPE Processor.
Computer
Matthew K. Farrens, Andrew R. Pleszkun
1991 A* conf
Strategies for Achieving Improved Processor Throughput.
ISCA
Matthew K. Farrens, Andrew R. Pleszkun
1990 A* conf
An evaluation of functional unit lengths for single-chip processors.
MICRO
Matthew K. Farrens, Andrew R. Pleszkun
1989 A* conf
Improving Performance of Small On-Chip Instruction Caches.
ISCA
Matthew K. Farrens, Andrew R. Pleszkun
1988 J jnl
Implementing Precise Interrupts in Pipelined Processors.
IEEE Trans. Computers
James E. Smith, Andrew R. Pleszkun
1988 A* conf
Multiple instruction issue and single-chip processors.
MICRO
Andrew R. Pleszkun, Gurindar S. Sohi
1988 A* conf
The Performance Potential of Multiple Functional Unit Processors.
ISCA
Andrew R. Pleszkun, Gurindar S. Sohi
1987 J jnl
On the Structural Locality of Reference in LISP List Access Streams.
Inf. Process. Lett.
Matthew Thazhuthaveetil, Andrew R. Pleszkun
1987 J jnl
The Architecture of Lisp Machines.
Computer
Andrew R. Pleszkun, Matthew Thazhuthaveetil
1987 A* conf
WISQ: A Restartable Architecture Using Queues.
ISCA
Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter
1986 A* conf
An Architecture for Efficient Lisp List Access.
ISCA
Andrew R. Pleszkun, Matthew Thazhuthaveetil
1986 — conf
Features of the Structured Memory Access (SMA) Architecture.
COMPCON
Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson
1985 A* conf
An algorithm for design rule checking on a multiprocessor.
DAC
George E. Bier, Andrew R. Pleszkun
1985 A* conf
Implementation of Precise Interrupts in Pipelined Processors.
ISCA
James E. Smith, Andrew R. Pleszkun
1985 A* conf
PIPE: A VLSI Decoupled Architecture.
ISCA
James R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young
1983 B conf
Structured Memory Access Architecture.
ICPP
Andrew R. Pleszkun, Edward S. Davidson
1982 — —
A Structured Memory Access Architecture
Andrew R. Pleszkun